Abstract: A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.

Abstract: A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.