Abstract: A memory tester for testing memory devices. The tester comprises a test header, an algorithmic pattern generator (APG) and a fault logic device. In the memory tester according to the invention successive data processing algorithms with minimum feedbacks are used. The APG generates test instructions wherein each instruction has fields controlling respective functional parts of the tester. The control signals are stored together with data signals in an instruction memory that provides high speed test pattern generation. For different memory types, the width of instruction memory varies.

Abstract: A processing architecture for performing a plurality of tasks comprises a conveyor of pipe stages, having a certain width comprising different fields including commands and operands, and a clock signal; wherein each pipe stage performs a certain part of an operation for each task of the plurality in a respective time slot.

Abstract: An adaptive equaliser comprises a variable filter, means for measuring a received signal and control means for adjusting the filter parameters, wherein the filter parameters are adjusted based on the width of the eye opening measured in the eye diagram of the received signal. The received signal is scanned at a variable voltage or current threshold to construct a digitised representation. This information is applied to establish the correct coefficients in an equalisation filter that compensates for the distortion of the channel. The filter may be arranged in the receiver, in the transmitter, or both in the transmitter and the receiver.

Abstract: The present invention relates to the reduction of timing uncertainty in high speed communications channel or interface and to a receiver and method using the same. The receiver according to the invention comprises a plurality of samplers for latching data. The invention provides improvements to the Bit Error rate versus channel and inherent register noise, as a result of employment of the characteristic of phase noise within the receiving registers to measure the characteristics of the channel and to compensate for variations in the channel by altering the timing characteristics of the signal.

Abstract: A transmission system and method for transmission of digital data with impedance matching at the terminal ends reduces reflected signals due to impedance mismatch at the terminating ends and due to impedance transition areas in the transmission line. The transmission system includes a transmission line having a driver end connected to a driving circuit and a receiving end connected to a receiving circuit, each said end having an adjustable termination means connected thereto On the driver end of the transmission line said adjustable termination means is incorporated in the driving circuit, while on the receiver end of the transmission line said adjustable termination means is connected in parallel with the receiving circuit. Thus, both the reflections produced on the ends of a transmission line and the reflections resulting from discontinuities within a transmission line will be terminated.

Abstract: The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips. A data transmission means for high-speed transmission of digital data is proposed, the data transmission means comprising: at least one driver for driving a transmission line; and a timing deskewing means connected thereto, wherein the timing deskewing means comprises a storage means for recording and storing information on skew caused by inter-symbol interference and cross-talk influence in the transmission line, for at least one data pattern transmitted through the transmission line; and an adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate for the above skew.

Abstract: The present invention relates to high speed communications, in particular, to an interface device between a transmitting device and a receiving device of a transmission system, wherein the transmitting device is capable of automatic compensation of cross-talk timing errors in the interface device, for a group of signals, by using information stored in a storage attached to that interface device. Preferably, the data stored in said storage comprises data on interconnections between said first and second plurality of terminals and data on crosstalk timing errors in said transmission lines relating to a specific data pattern, for each of said stored interconnection.

Abstract: A high precision receiver with a means to reduce or compensate the skew caused by the receiver's hysteresis by using a dynamic reference that is varied depending on a current output signal. To avoid oscillation, the reference signal can be switched over with a certain delay.

Abstract: The present invention relates generally to data processing systems, in particular, to high speed data communication and chip-to-chip data transfer.

Abstract: The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips.

Abstract: The present invention relates to the reducing of timing uncertainties in high-performance digital circuitry. More specifically, the present invention relates to a timing control means and method for minimizing timing uncertainties due to skew and jitter. A means for the compensation of timing errors in multiple channel electronic devices comprising at least one register having a plurality of channels comprises: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers; wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's timing, the feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence and a set of delay means which uses the detected values of probability to generate a feedback signal.