Abstract: A self-timed implementation of single-stage and two-stage self-timed trigger circuits with single-rail data input is provided. This is achieved by a circuit containing storage unit with element indicating transition termination, single-rail data input, control input, data output, and indication output, into which a conversion unit is added which converts single-rail data input and control input signals and has data input, control input, data output and control output. An additional feedback output allows for speeding-up transition of device, which is a source of the single-rail data input of the trigger.

Abstract: The invention describes self-timed RS-trigger with the enhanced noise immunity. Declared effect is achieved due to that circuit containing storage unit (1), indication unit (2), paraphase data input (3, 4), paraphase data output (5, 6), and indication output (7), is modified by adding two inverters (8, 9) and preindication unit (10). Inverters increase output capability of the trigger's paraphase data output and provide an electric isolation of the outputs of the storage unit from an external environment that leads to increasing immunity of the data stored in the trigger to influence of noises at signal wires. The preindication unit provides the trigger's indicatability.

Abstract: The invention describes self-timed RS-trigger with the enhanced noise immunity. Declared effect is achieved due to that circuit containing storage unit (1), indication unit (2), paraphase data input (3, 4), paraphase data output (5, 6), and indication output (7), is modified by adding two inverters (8, 9) and preindication unit (10). Inverters increase output capability of the trigger's paraphase data output and provide an electric isolation of the outputs of the storage unit from an external environment that leads to increasing immunity of the data stored in the trigger to influence of noises at signal wires. The preindication unit provides the trigger's indicatability.

Abstract: A self-timed implementation of single-stage and two-stage self-timed triggers with single-rail data input is provided. This is achieved by a circuit containing storage unit with element indicating transition termination, single-rail data input, control input, data output, and indication output, into which a conversion unit is added which converts single-rail data input and control input signals and has data input, control input, data output and control output. An additional feedback output allows for speeding-up transition of device, which is a source of the single-rail data input of the trigger.