Patents by Inventor Igor Chirashnya
Igor Chirashnya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7287063Abstract: An storage area network (SAN) has a manager digital data processor that includes a first element that maintains a first representation of the SAN and a second element that maintains a second representation of the SAN. The first element generates notifications of events in the SAN, e.g., addition or removal of components or relationships between components, and includes with them data pertaining to the event. The second element responds to such notifications and data by updating the second representation. That data is preferably sufficient for the second element to update the second representation without further reference to information contained in the representation.Type: GrantFiled: October 5, 2001Date of Patent: October 23, 2007Assignee: International Business Machines CorporationInventors: Duane Mark Baldwin, Igor Chirashnya, Gregory John Knight, David Lynn Merbach, Kirill Shoikhet, William Roy Yonker
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Patent number: 7113988Abstract: A method for diagnosis of a system made up of a plurality of interlinked modules includes receiving an alarm from the system indicative of a fault in one of the modules. Responsive to the alarm, a causal network is constructed associating the fault with malfunctions in one or more of the modules that may have led to the fault and relating a conditional probability of the fault to respective probabilities of the malfunctions. Based on the alarm and the causal network, at least one of the probabilities of the malfunctions is updated. A diagnosis of the alarm is proposed responsive to the updated probabilities.Type: GrantFiled: June 28, 2001Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: Igor Chirashnya, Leah Shalev, Kirill Shoikhet
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Patent number: 7050437Abstract: A network interface device includes receive logic, which is coupled to receive from a network a sequence of data packets, each packet including respective header data. A protocol processor is coupled to read and process the header data so as to identify a group of the received packets that contain respective fragments of a data frame, the fragments having a fragment order within the data frame. Host interface logic is coupled to a host memory accessible by a host processor, and is controlled by the protocol processor so as to allocate space for the data frame in the host memory, and to reassemble the fragments of the data frame in the fragment order in the space allocated in the host memory.Type: GrantFiled: March 16, 2001Date of Patent: May 23, 2006Assignee: International Business Machines CorporationInventors: Hrvoje Bilic, Giora Biran, Igor Chirashnya, Georgy Machulsky, Claudiu Schiller, Tal Sostheim
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Patent number: 6947430Abstract: A network interface device includes host interface logic, arranged to receive from a host processor a frame of outgoing data that includes outgoing header information and outgoing payload data, and to separate the header information from the payload data. A transmit protocol processor is coupled to read and process the outgoing header information from the outgoing header memory so as to generate at least one outgoing packet header in accordance with a predetermined network protocol. Transmit logic is coupled to receive and associate the at least one outgoing packet header with the outgoing payload data from the outgoing data memory, so as to generate at least one outgoing data packet for transmission over a network in accordance with the protocol.Type: GrantFiled: March 16, 2001Date of Patent: September 20, 2005Assignee: International Business Machines CorporationInventors: Hrvoje Bilic, Giora Biran, Igor Chirashnya, Georgy Machulsky, Claudiu Schiller, Tal Sostheim
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Publication number: 20030149761Abstract: An storage area network (SAN) has a manager digital data processor that includes a first element that maintains a first representation of the SAN and a second element that maintains a second representation of the SAN. The first element generates notifications of events in the SAN, e.g., addition or removal of components or relationships between components, and includes with them data pertaining to the event. The second element responds to such notifications and data by updating the second representation. That data is preferably sufficient for the second element to update the second representation without further reference to information contained in the representation.Type: ApplicationFiled: October 5, 2001Publication date: August 7, 2003Inventors: Duane Mark Baldwin, Igor Chirashnya, Gregory John Knight, David Lynn Merbach, Kirill Shoikhet, William Roy Yonker
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Patent number: 6601195Abstract: In a computer network system that includes a multiplicity of nodes interconnected by a network of switches, wherein the nodes are linked to the network by respective data link adapters, a method for testing the adapters. One of the nodes is selected to serve as a destination node, and data are conveyed at a controlled rate from a plurality of the nodes, other than the destination node, through the respective adapters to the destination node. An error is detected in the data conveyed from one of the nodes so as to identify a fault in the adapter of that node.Type: GrantFiled: September 9, 1999Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventors: Igor Chirashnya, Tal Sostheim
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Patent number: 6598179Abstract: A method for diagnosing faults in a computer-based system. A log of errors of different kinds that have been recorded in the system is read, and errors of those kinds that are relevant to one or more predetermined types of faults that can occur in the system are selected from the log. The selected errors are filtered so as to compose one or more events, each event comprising one or more occurrences of one or more of the relevant kinds of the errors. The composed events are analyzed to reach an assessment that at least one of the predetermined types of faults has occurred.Type: GrantFiled: March 31, 2000Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: Igor Chirashnya, Doron Erblich, Raanan Gewirtesman
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Patent number: 6560720Abstract: In a computer network system that includes a multiplicity of nodes interconnected by a network of switches, wherein data are normally conveyed in the network according to predetermined conventions, a method for simulation testing of the system. One of the nodes is selected to serve as an error injector and injects data into the network in a manner that violates the predetermined conventions, so as to simulate an error condition in the system. Operation of the system is observed following the injection of the data so as to evaluate a response of the system to the error condition.Type: GrantFiled: September 9, 1999Date of Patent: May 6, 2003Assignee: International Business Machines CorporationInventors: Igor Chirashnya, George Machulsky, Rony Ross, Leah Shalev
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Patent number: 6487208Abstract: In a computer network system that includes a multiplicity of nodes interconnected by a network of switches, each switch having multiple ports, a method for testing one of the switches includes assigning a respective one of the nodes to each of a plurality of the ports of the switch being tested. The network is configured so that the switch being tested is substantially isolated from data flow from and to the nodes in the network that are not assigned to the ports of the switch. Data are conveyed at a controlled rate between two or more of the assigned nodes through the respective ports, and behavior of the switch is observed in response to the data being conveyed.Type: GrantFiled: September 9, 1999Date of Patent: November 26, 2002Assignee: International Business Machines CorporationInventors: Igor Chirashnya, Nick Rash, Leah Shalev
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Publication number: 20020019870Abstract: A method for diagnosis of a system made up of a plurality of interlinked modules includes receiving an alarm from the system indicative of a fault in one of the modules. Responsive to the alarm, a causal network is constructed associating the fault with malfunctions in one or more of the modules that may have led to the fault and relating a conditional probability of the fault to respective probabilities of the malfunctions. Based on the alarm and the causal network, at least one of the probabilities of the malfunctions is updated. A diagnosis of the alarm is proposed responsive to the updated probabilities.Type: ApplicationFiled: June 28, 2001Publication date: February 14, 2002Applicant: International Business Machines CorporationInventors: Igor Chirashnya, Leah Shalev, Kirill Shoikhet
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Publication number: 20010053148Abstract: A network interface device includes host interface logic, arranged to receive from a host processor a frame of outgoing data that includes outgoing header information and outgoing payload data, and to separate the header information from the payload data. A transmit protocol processor is coupled to read and process the outgoing header information from the outgoing header memory so as to generate at least one outgoing packet header in accordance with a predetermined network protocol. Transmit logic is coupled to receive and associate the at least one outgoing packet header with the outgoing payload data from the outgoing data memory, so as to generate at least one outgoing data packet for transmission over a network in accordance with the protocol.Type: ApplicationFiled: March 16, 2001Publication date: December 20, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hrvoje Bilic, Giora Biran, Igor Chirashnya, Georgy Machulsky, Claudiu Schiller, Tal Sostheim
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Publication number: 20010048681Abstract: A network interface device includes receive logic, which is coupled to receive from a network a sequence of data packets, each packet including respective header data. A protocol processor is coupled to read and process the header data so as to identify a group of the received packets that contain respective fragments of a data frame, the fragments having a fragment order within the data frame. Host interface logic is coupled to a host memory accessible by a host processor, and is controlled by the protocol processor so as to allocate space for the data frame in the host memory, and to reassemble the fragments of the data frame in the fragment order in the space allocated in the host memory.Type: ApplicationFiled: March 16, 2001Publication date: December 6, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hrvoje Bilic, Giora Biran, Igor Chirashnya, Georgy Machulsky, Claudiu Schiller, Tal Sostheim