Patents by Inventor Igor Chourkin

Igor Chourkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7823112
    Abstract: A method, software, and system for placing circuit elements and routing wires. The method, software, and system generally include the steps of (a) determining a boundary condition for signal paths between components in a circuit, wherein each of the components receives a clock signal and the signal paths include n wires and (n?1) circuit elements in alternating serial communication between the components, n being 2 or more; and (b) placing the circuit elements and routing the wires between the comments and the circuit elements such that no signal path in the circuit exceeds the boundary condition. In preferred embodiments, the boundary condition is a maximum length, and the method further includes placing the clocked components in a floor plan such that no signal path can exceed the boundary condition. The present invention advantageously ensures that timing requirements for signal paths between clocked circuit components are met automatically.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: October 26, 2010
    Assignee: Golden Gate Technology, Inc.
    Inventors: Mikhail Makarov, Igor Chourkin, Mikhail Komarov, Boris Ginzburg
  • Patent number: 7178124
    Abstract: A method, algorithm, software, architecture and system for placing circuit components and routing wires. The method and algorithm generally include (a) placing components in an array of allowed locations, wherein each of the components receives a clock signal and each of the allowed locations is about the same distance from a first nearest neighbor along at least a first axis as are other allowed locations along said first axis, and (b) one of the following: (i) independently routing a plurality of combinational paths from at least two components to at least two other components, (ii) routing the clock signal to the components, or both (i) and (ii). The present method, algorithm, software, architecture and system advantageously reduce power and/or current consumption in integrated circuits, improve uniformity of timing for signal paths between clocked circuit components, and/or ensure that timing requirements for signal paths between clocked circuit components are met automatically.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: February 13, 2007
    Assignee: Golden Gate Technology, Inc.
    Inventors: Mikhail Makarov, Igor Chourkin, Mikhail Komarov, Boris Ginzburg