Abstract: A hardware implementation of the Transfer Control Protocol/Internet Protocol (TCP/IP) software stack comprising multiple modular hardware gate level blocks used to implement the discrete functions required for link termination. These modules are designed using low power techniques to minimize the power required to achieve the data processing required by TCP/IP. These hardware blocks are modular so that they can be run at varying clock rates, or have various supply voltages provided thereto, depending on the throughput requirement of each block. Furthermore, at design time of each programmable hardware circuit (PHC) functional circuit blocks (FCBs) used to implement functionality within the PHC are optimized in accordance with predetermined parameters in order to obtain predetermined programmed PHC functionality, such as reduced power consumption or high bandwidth data throughput.