Patents by Inventor Igor Gorodetsky

Igor Gorodetsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10129329
    Abstract: An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 13, 2018
    Assignee: Cray Inc.
    Inventors: Edwin L. Froese, Eric P. Lundberg, Igor Gorodetsky, Howard Pritchard, Charles Giefer, Robert L. Alverson, Duncan Roweth
  • Publication number: 20160077997
    Abstract: An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.
    Type: Application
    Filed: October 13, 2015
    Publication date: March 17, 2016
    Inventors: Edwin L. Froese, Eric P. Lundberg, Igor Gorodetsky, Howard Pritchard, Charles Giefer, Robert L. Alverson, Duncan Roweth
  • Patent number: 9185034
    Abstract: A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Igor Gorodetsky, Walter James Reinhard
  • Patent number: 9160607
    Abstract: An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 13, 2015
    Assignee: Cray Inc.
    Inventors: Edwin L. Froese, Eric P. Lundberg, Igor Gorodetsky, Howard Pritchard, Charles Giefer, Robert L. Alverson, Duncan Roweth
  • Publication number: 20140314083
    Abstract: A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
    Type: Application
    Filed: February 18, 2014
    Publication date: October 23, 2014
    Inventors: Igor Gorodetsky, Walter James Reinhard
  • Patent number: 8677025
    Abstract: A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: March 18, 2014
    Assignee: Intel Corporation
    Inventors: Igor Gorodetsky, Walter James Reinhard
  • Patent number: 8260969
    Abstract: A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: September 4, 2012
    Assignee: Intel Corporation
    Inventors: Igor Gorodetsky, Walter James Reinhard
  • Publication number: 20120203928
    Abstract: A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
    Type: Application
    Filed: April 19, 2012
    Publication date: August 9, 2012
    Inventors: Igor Gorodetsky, Walter James Reinhard
  • Publication number: 20100138562
    Abstract: A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
    Type: Application
    Filed: February 2, 2010
    Publication date: June 3, 2010
    Applicant: CRAY CANADA CORPORATION
    Inventors: Igor GORODETSKY, Walter James REINHARD
  • Patent number: 7685319
    Abstract: A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: March 23, 2010
    Assignee: Cray Canada Corporation
    Inventors: Igor Gorodetsky, Walter James Reinhard
  • Patent number: 7606933
    Abstract: A high performance computer system has a number of compute nodes interconnected by an inter-node communication network. Each compute node has a local packetized interconnect coupled to the inter-node communication network by an interface. Data packets on the local packetized interconnect of a sending node may be delivered to a destination in a receiving node by addressing them to addresses associated with the network interface and tunneling the packets through the inter-node communication network to the receiving node.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: October 20, 2009
    Assignee: Cray Canada Corporation
    Inventors: Walter James Reinhard, Igor Gorodetsky
  • Publication number: 20060067318
    Abstract: A high performance computer system has compute nodes interconnected by an inter-node communication network. The compute nodes include local packetized interconnects. Shared memory between compute nodes is emulated by tunneling packetized interconnect packets between the compute nodes. A memory region on one of the compute nodes is used as a window into a memory region in another compute node. Special registers may be provided to expedite remote operations on small amounts of data.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 30, 2006
    Applicant: Cray Canada Inc.
    Inventors: Igor Gorodetsky, Walter Reinhard
  • Publication number: 20050188105
    Abstract: A high performance computer system has a number of compute nodes interconnected by an inter-node communication network. Each compute node has a local packetized interconnect coupled to the inter-node communication network by an interface. Data packets on the local packetized interconnect of a sending node may be delivered to a destination in a receiving node by addressing them to addresses associated with the network interface and tunneling the packets through the inter-node communication network to the receiving node.
    Type: Application
    Filed: February 11, 2004
    Publication date: August 25, 2005
    Applicant: OctigaBay Systems Corporation
    Inventors: Walter Reinhard, Igor Gorodetsky
  • Publication number: 20050132089
    Abstract: Compute nodes in a high performance computer system are interconnected by an inter-node communication network. Each compute node has a network interface coupled directly to a CPU by a dedicated full-duplex packetized interconnect. Data may be exchanged between compute nodes using eager or rendezvous protocols. The network interfaces may include facilities to manage data transfer between computer nodes.
    Type: Application
    Filed: March 1, 2004
    Publication date: June 16, 2005
    Applicant: Octigabay Systems Corporation
    Inventors: Kent Bodell, James Reinhard, Igor Gorodetsky, Josef Roehrl