Patents by Inventor Igor Jekauc

Igor Jekauc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for monitoring precision of water placement alignment
    Patent number: 7381576
    Abstract: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the thickness of the insulating film to determine etch rates for the film at selected locations on the surface of the semiconductor wafer, and based on the determined etch rates, determining misalignment of the semiconductor wafer.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: June 3, 2008
    Assignee: Infineon Technologies Richmond, LP.
    Inventor: Igor Jekauc
  • Method and apparatus for monitoring precision of wafer placement alignment
    Publication number: 20070037301
    Abstract: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the thickness of the insulating film to determine etch rates for the film at selected locations on the surface of the semiconductor wafer, and based on the determined etch rates, determining misalignment of the semiconductor wafer.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 15, 2007
    Inventor: Igor Jekauc
  • Method and device for minimizing multi-layer microscopic and macroscopic alignment errors
    Patent number: 6881592
    Abstract: A method of aligning a second layer to a first layer of a semiconductor structure by forming a first layer of a wafer having a distinguished feature via a first etching process that employs a first ionized gas generating machine. Forming a second layer having a circuit pattern via a second etching process that employs a second ionized gas generating machine, wherein the forming the second layer includes minimizing relative shifting between the distinguished feature located at an edge of the wafer for the first layer and the second circuit pattern located at the edge of the wafer for the second layer.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: April 19, 2005
    Assignee: Infineon Technologies Richmond, LP
    Inventors: William Roberts, Diem-Thy Ngu-Uyen Tran, Paul Jowett, Nicholas Clements, Igor Jekauc, Karen Anne Davidson, Winifried Sabisch
  • Method and device for minimizing multi-layer microscopic and macroscopic alignment errors
    Publication number: 20040072447
    Abstract: A method of aligning a second layer to a first layer of a semiconductor structure by forming a first layer of a wafer having a distinguished feature via a first etching process that employs a first ionized gas generating machine. Forming a second layer having a circuit pattern via a second etching process that employs a second ionized gas generating machine, wherein the forming the second layer includes minimizing relative shifting between the distinguished feature located at an edge of the wafer for the first layer and the second circuit pattern located at the edge of the wafer for the second layer.
    Type: Application
    Filed: June 3, 2003
    Publication date: April 15, 2004
    Inventors: William Roberts, Diem-Thy Ngu-Uyen Tran, Paul Jowett, Nicholas Clements, Igor Jekauc, Karen Anne Davidson, Winfried Sabisch