Patents by Inventor Igor Koutnetsov

Igor Koutnetsov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
    Patent number: 7505321
    Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 17, 2009
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher Petti, Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli, Igor Koutnetsov
  • Method for fabricating programmable memory array structures incorporating series-connected transistor strings
    Patent number: 7005350
    Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: February 28, 2006
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Roy E. Scheuerlein, Alper Ilkbahar, Luca Fasoli, Igor Koutnetsov, Christopher Petti