Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.

Abstract: A method of making a semiconductor device is provided. The method includes forming a deep well (DWELL) and a well (WELL) in a first region of a substrate, the WELL adjacent a surface of the substrate so that an interface between the WELL and DWELL is exposed on the surface of the substrate. A channel for a DEMOS transistor is formed in the first region over the interface and includes a first channel formed in the WELL and a second channel formed in the DWELL. A gate layer is deposited and patterned to concurrently form in the first region a first gate for the DEMOS transistor and in a second region a second gate for an ESD device. Dopants are implanted in the first and second regions to concurrently form a drain extension of the DEMOS transistor, and an ESD diffusion region of the ESD device.

Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. The method begins with depositing and patterning a first photoresist mask over a surface of a substrate to expose a N-SONOS region, and implanting a channel for a NSONOS device through a first pad oxide, followed by depositing and patterning a second photoresist mask to expose a P-SONOS region, and implanting a channel for a PSONOS device through a second pad oxide. Next, a number of Nwells are concurrently implanted for the PSONOS device and a PMOS device in a core region of the substrate. Finally, the first and second pad oxides, which were left in place to separate the P-SONOS region and the N-SONOS region from the first and second photoresist masks, are concurrently removed. In one embodiment, implanting the Nwells includes implanting a single, contiguous deep Nwell for the PSONOS and PMOS device.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. The method begins with depositing and patterning a first photoresist mask over a surface of a substrate to expose a N-SONOS region, and implanting a channel for a NSONOS device through a first pad oxide, followed by depositing and patterning a second photoresist mask to expose a P-SONOS region, and implanting a channel for a PSONOS device through a second pad oxide. Next, a number of Nwells are concurrently implanted for the PSONOS device and a PMOS device in a core region of the substrate. Finally, the first and second pad oxides, which were left in place to separate the P-SONOS region and the N-SONOS region from the first and second photoresist masks, are concurrently removed. In one embodiment, implanting the Nwells includes implanting a single, contiguous deep Nwell for the PSONOS and PMOS device.

Abstract: A method of making a semiconductor device is provided. The method includes forming a deep well (DWELL) and a well (WELL) in a first region of a substrate, the WELL adjacent a surface of the substrate so that an interface between the WELL and DWELL is exposed on the surface of the substrate. A channel for a DEMOS transistor is formed in the first region over the interface and includes a first channel formed in the WELL and a second channel formed in the DWELL. A gate layer is deposited and patterned to concurrently form in the first region a first gate for the DEMOS transistor and in a second region a second gate for an ESD device. Dopants are implanted in the first and second regions to concurrently form a drain extension of the DEMOS transistor, and an ESD diffusion region of the ESD device.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

Abstract: A memory structure is provided including an array of non-volatile memory (NVM) cells arranged in rows and columns, each cell including a NVM transistor having a body bias terminal coupled to body bias supply. The memory structure further includes a control system to control the body bias supply to adjust a body bias voltage coupled to the body bias terminals during read operations of the memory structure to compensate for shifts in threshold voltages (VTH) of the NVM transistors to maintain a read current window (IRCW) between a cell in which the NVM transistor is ON and a sum of leakage current through cells in which the NVM transistor is OFF. Methods of operating the memory structure are also described.

Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.

Abstract: A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.

Abstract: A circuit including both drain-extended metal-oxide-semiconductor (DEMOS) and low-voltage metal-oxide-semiconductor (LV_MOS) devices and methods of manufacturing the same are provided. In one embodiment, DEMOS device includes a first channel, a gate, a second channel, and a drain extension, wherein the second channel is split into a first portion and a second portion, and wherein the first portion of the second channel stops under the gate and is spaced away from the drain extension. Other embodiments are also described.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.