Patents by Inventor Igor Kucherenko
Igor Kucherenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9208330Abstract: An apparatus having a first memory circuit, a plurality of arithmetic modules, and a plurality of second memory circuits. The first memory circuit may be configured to read or write data to or from a host. The plurality of arithmetic modules each may be configured to be enabled or disabled in response to control signals received from the first memory circuit. The plurality of second memory circuits may be configured to read or write data to or from the first memory circuit through a data exchange layer. The arithmetic modules provide cryptographic protection of the data.Type: GrantFiled: February 10, 2014Date of Patent: December 8, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Krishnan Srinivasan, Igor Kucherenko, Nikola Radovanovic
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Publication number: 20150220744Abstract: An apparatus having a first memory circuit, a plurality of arithmetic modules, and a plurality of second memory circuits. The first memory circuit may be configured to read or write data to or from a host. The plurality of arithmetic modules each may be configured to be enabled or disabled in response to control signals received from the first memory circuit. The plurality of second memory circuits may be configured to read or write data to or from the first memory circuit through a data exchange layer. The arithmetic modules provide cryptographic protection of the data.Type: ApplicationFiled: February 10, 2014Publication date: August 6, 2015Applicant: LSI CORPORATIONInventors: Krishnan Srinivasan, Igor Kucherenko, Nikola Radovanovic
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Patent number: 8831221Abstract: In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks.Type: GrantFiled: September 28, 2010Date of Patent: September 9, 2014Assignee: LSI CorporationInventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav Ivanovic, Igor Kucherenko, Alexei Galatenko
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Patent number: 8516425Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.Type: GrantFiled: July 9, 2012Date of Patent: August 20, 2013Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Publication number: 20120278783Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Applicant: LSI CORPORATIONInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 8239813Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.Type: GrantFiled: June 30, 2011Date of Patent: August 7, 2012Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Publication number: 20120076298Abstract: In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Inventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav Ivanovic, Igor Kucherenko, Alexei Galatenko
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Publication number: 20110258587Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: LSI CORPORATIONInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 7996804Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.Type: GrantFiled: January 17, 2008Date of Patent: August 9, 2011Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Publication number: 20090187873Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin