Abstract: A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal.

Abstract: A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal.

Abstract: A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal.

Abstract: A non-volatile memory cell with high bit density is disclosed. Embodiments include: providing a transistor having a wordline gate structure over a substrate, first and second floating gate structures proximate opposite sides of the wordline gate structure, and first and second diffusion regions in the substrate, wherein the wordline gate structure, the first floating gate structure, and the second floating gate structure are laterally between the first and second diffusion regions; and providing a capacitor having first, second, and third control gate structures over the substrate, a third floating gate structure between the first and second control gate structures, a fourth floating gate structure between the second and third control gate structures, and third and fourth diffusion regions in the substrate, wherein the first, second, and third control gate structures are laterally between the third and fourth diffusion regions.

Abstract: A non-volatile memory cell with high bit density is disclosed. Embodiments include: providing a transistor having a wordline gate structure over a substrate, first and second floating gate structures proximate opposite sides of the wordline gate structure, and first and second diffusion regions in the substrate, wherein the wordline gate structure, the first floating gate structure, and the second floating gate structure are laterally between the first and second diffusion regions; and providing a capacitor having first, second, and third control gate structures over the substrate, a third floating gate structure between the first and second control gate structures, a fourth floating gate structure between the second and third control gate structures, and third and fourth diffusion regions in the substrate, wherein the first, second, and third control gate structures are laterally between the third and fourth diffusion regions.