Abstract: A system and associated method for simulating a storage device. In the system and method, a set of simulation entities (SEs) is provided including a host SE and storage component SEs corresponding to hardware and software components of the storage device to be simulated, SEs from the set of the SEs are selected, a logical relationship is determined between the selected SEs, sequential messages are propagated between the selected SEs and to the simulation core engine which determine whether conditions for a simulation are complete, and simulations are performed using the selected SEs.

Abstract: Superblock linkage systems and methods use asymmetric die packages. A controller of a memory system selects a set number of dies in a plurality of memory packages, the set number of dies being less than the total number of dies in the plurality of memory packages. The plurality of memory packages includes multiple memory packages and at least one memory package, each of the multiple memory packages having a first number of dies, the one memory package having a second number of dies. Further, the controller: generates a superblock including physical blocks with the same number or different numbers on the selected dies; repeats the selection and generation to generate multiple superblocks; and performs an operation on a superblock selected from among the multiple superblocks.

Abstract: Memory systems and components thereof execute an improved garbage collection (GC) strategy in the case of multiple sudden power offs (SPOs). Such a memory system comprises a memory device including single-level cell (SLC) memory blocks grouped into super blocks (SLC SBs) and multi-level cell (MLC) memory blocks grouped into SBs (MLC SBs); and a memory controller to execute a flash translation layer (FTL) to perform a garbage collection (GC) operation. The memory controller executes the GC operation after a sudden power off (SPO) by determining each MLC SB with user data opened before the SPO to be an unsafe super block (UB), copying data from pages in a select one of the UBs to pages in the SLC SBs, and copying data from the pages in the SLC SBs to pages in a select MLC SB not determined to be a UB.

Abstract: Methods and systems are provided for compression and reconstruction of system data. A controller of a memory system includes a compression component for searching for a pattern of an array of system data including a plurality of elements and compressing the array of system data based on the pattern. The array of system data includes neighbor elements corresponding to a first pattern, among the plurality of elements. The compressed system data includes: first information including a first bit indicating a first content; and second information including a first bitmap, each bit of the first bitmap indicating whether a corresponding element is a first element among the neighbor elements of the first pattern.

Abstract: Techniques are presented that more efficiently calculate data path protection (DPP) parity. Firmware is advantageously used for such calculation with limited or no calls to a DPP engine, depending on the type of host data. The techniques use linear code properties of the type of host data to enable the firmware to calculate DPP parity faster than using the DPP engine for all calculations.

Abstract: Methods and instruction sets are provided for performing event management in an embedded system such as a memory system including a memory device and a controller. The controller divides a group of objects, among a plurality of groups of objects, into a plurality of subgroups, each subgroup including a plurality of objects. The controller counts a number of times that each of the objects is affected by external event using an event counter, updates a count value of each of the subcounters each time an object in the corresponding subgroup is affected by the external event, updates a count value of a main counter each time one of the subcounters reaches a count value equal to a first threshold value; and performing system action on the group of objects, when the count value of the main counter is equal to a second threshold value.

Abstract: Techniques are presented that more efficiently calculate data path protection (DPP) parity. Firmware is advantageously used for such calculation with limited or no calls to a DPP engine, depending on the type of host data. The techniques use linear code properties of the type of host data to enable the firmware to calculate DPP parity faster than using the DPP engine for all calculations.

Abstract: Memory systems and components thereof execute an improved garbage collection (GC) strategy in the case of multiple sudden power offs (SPOs). Such a memory system comprises a memory device including single-level cell (SLC) memory blocks grouped into super blocks (SLC SBs) and multi-level cell (MLC) memory blocks grouped into SBs (MLC SBs); and a memory controller to execute a flash translation layer (FTL) to perform a garbage collection (GC) operation. The memory controller executes the GC operation after a sudden power off (SPO) by determining each MLC SB with user data opened before the SPO to be an unsafe super block (UB), copying data from pages in a select one of the UBs to pages in the SLC SBs, and copying data from the pages in the SLC SBs to pages in a select MLC SB not determined to be a UB.

Abstract: Methods and systems are provided for compression and reconstruction of system data. A controller of a memory system includes a compression component for searching for a pattern of an array of system data including a plurality of elements and compressing the array of system data based on the pattern. The array of system data includes neighbor elements corresponding to a first pattern, among the plurality of elements. The compressed system data includes: first information including a first bit indicating a first content; and second information including a first bitmap, each bit of the first bitmap indicating whether a corresponding element is a first element among the neighbor elements of the first pattern.

Abstract: Methods and instruction sets are provided for performing event management in an embedded system such as a memory system including a memory device and a controller. The controller divides a group of objects, among a plurality of groups of objects, into a plurality of subgroups, each subgroup including a plurality of objects. The controller counts a number of times that each of the objects is affected by external event using an event counter, updates a count value of each of the subcounters each time an object in the corresponding subgroup is affected by the external event, updates a count value of a main counter each time one of the subcounters reaches a count value equal to a first threshold value; and performing system action on the group of objects, when the count value of the main counter is equal to a second threshold value.