Abstract: A passive optical network (PON) processor comprises a packet processor for processing packets belonging to a certain flow through a plurality of processing stages of a programmable data-path; a microprocessor-data for performing one or more user-defined functions in the programmable data-path on designated packets belonging to the certain flow, wherein packets of respective flows to be processed by the microprocessor-data are designated in a flow table; a microprocessor-control for managing connections handled by the PON processor; a data-path bus for connecting the packet processor and the microprocessor-data, wherein the designated packets are transferred between the packet processor and the microprocessor-data on the data-path bus; and a control-path bus for connecting the packet processor and the microprocessor-control.

Abstract: A passive optical network (PON) processor comprises a packet processor for processing packets belonging to a certain flow through a plurality of processing stages of a programmable data-path; a microprocessor-data for performing one or more user-defined functions in the programmable data-path on designated packets belonging to the certain flow, wherein packets of respective flows to be processed by the microprocessor-data are designated in a flow table; a microprocessor-control for managing connections handled by the PON processor; a data-path bus for connecting the packet processor and the microprocessor-data, wherein the designated packets are transferred between the packet processor and the microprocessor-data on the data-path bus; and a control-path bus for connecting the packet processor and the microprocessor-control.

Abstract: Method and system for managing a buffers pool. The system may include a first processor coupled to a general memory having allocation ring and de-allocation ring portions; and a second processor to perform internal accounting of pointer(s) buffer(s). The second processor has an internal storage array logically divided into first and second storage spaces. The second processor releases temporarily un-required buffer(s) pointer(s) to the first storage space, or to the second storage space if the first storage space is full. The second processor utilizes allocated buffer(s) pointer(s) accumulated in the first storage space. The second processor is to cause a DMA engine to move a bulk of two or more buffer(s) pointer(s) from the allocation ring to the first storage space, and to move a bulk of two or more buffer(s) pointer(s) from the second storage space to the de-allocation ring.

Abstract: A system including a first processor functionally coupled to a general memory having allocation ring and de-allocation ring portions for allocating and de-allocating buffer(s) pointer(s), respectively, and a second processor having an internal storage array logically divided into a first storage space, for holding buffer(s) pointer(s) allocated for (and optionally buffer(s) pointer(s) released by) the second processor, and a second storage space, for holding buffer(s) pointer(s) de-allocated by the second processor. The second processor may be adapted to cause a DMA engine to move a bulk of buffer(s) pointer(s) from the allocation ring to the first storage space responsive to consuming all buffer pointers in a current first storage part in the first storage space, and a bulk of buffer(s) pointer(s) from the second storage space to the de-allocation ring responsive to releasing, for example, two pointers into the second storage space.

Abstract: A method and system to minimize the potential of jitter buffer underflow/overflow resulting from a difference in sampling rates of an audio encoder and an audio decoder are disclosed herein. The difference in sampling rates, or clock skew, can be determined from a difference between an actual amount of data stored in a jitter buffer and the desired, or threshold, amount. A subset of packets from a sequence of packets output to the audio decoder can be altered to compensate for the clock skew, whereby the amount of data associated with the subset of packets is decreased when the sampling rate of the encoder is greater than the sampling rate of the decoder, and the amount of data is increased when the sampling rate of the encoder is less than the sampling rate of the decoder. The present invention finds particular advantage in providing audio data via a packet-switched network.

Abstract: A method and system to minimize the potential of jitter buffer underflow/overflow resulting from a difference in sampling rates of an audio encoder and an audio decoder are disclosed herein. The difference in sampling rates, or clock skew, can be determined from a difference between an actual amount of data stored in a jitter buffer and the desired, or threshold, amount. A subset of packets from a sequence of packets output to the audio decoder can be altered to compensate for the clock skew, whereby the amount of data associated with the subset of packets is decreased when the sampling rate of the encoder is greater than the sampling rate of the decoder, and the amount of data is increased when the sampling rate of the encoder is less than the sampling rate of the decoder. The present invention finds particular advantage in providing audio data via a packet-switched network.