Patents by Inventor Igor V. Kucherenko

Igor V. Kucherenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low depth combinational finite field multiplier
    Patent number: 9417847
    Abstract: A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Sergey B. Gashkov, Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav D. Ivanovic, Anatoly A. Chasovshikh, Alexei V. Galatenko, Igor V. Kucherenko
  • LOW DEPTH COMBINATIONAL FINITE FIELD MULTIPLIER
    Publication number: 20120226731
    Abstract: A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.
    Type: Application
    Filed: September 13, 2011
    Publication date: September 6, 2012
    Inventors: Sergey B. Gashkov, Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav D. Ivanovic, Anatoly A. Chasovshikh, Alexei V. Galatenko, Igor V. Kucherenko