Patents by Inventor Igor Voks
Igor Voks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240411680Abstract: Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.Type: ApplicationFiled: June 6, 2023Publication date: December 12, 2024Inventors: Gil Kremer, Roee Moyal, Igor Voks, Liel Peled, Eliel Peretz, Ariel Shahar
-
Publication number: 20240281292Abstract: A device includes a transceiver coupled to a processing device. The processing device is to determine a first time for executing an operation associated with a work execution agent of a plurality of work execution agent. The processing device is further to receive a latency measurement associated with the work execution agent responsive to transmitting the request. The latency measurement is calculated after executing a previous operation associated with the work execution agent at the device. The processing device is also to modify the first time to a second time for executing the operation responsive to receiving the latency measurement.Type: ApplicationFiled: February 16, 2023Publication date: August 22, 2024Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Shay Aisman, Ariel Almog, Eliel Peretz, Igor Voks
-
Publication number: 20240193106Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.Type: ApplicationFiled: February 19, 2024Publication date: June 13, 2024Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
-
Patent number: 11940933Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.Type: GrantFiled: March 2, 2021Date of Patent: March 26, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
-
Patent number: 11762773Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.Type: GrantFiled: July 13, 2022Date of Patent: September 19, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks
-
Publication number: 20230251899Abstract: In one embodiment, a system includes a peripheral device including a hardware clock, and processing circuitry to read a given work request entry stored with a plurality of work request entries in at least one work queue in a memory, the given work request entry including timing data and an operator, the timing data being indicative of a time at which a work request should be executed, retrieve a clock value from the hardware clock, and execute the work request with a workload while execution of the work request is timed responsively to the timing data and the operator and the retrieved clock value.Type: ApplicationFiled: February 9, 2022Publication date: August 10, 2023Inventors: Dotan David Levi, Daniel Marcovitch, Natan Manevich, Wojciech Wasko, Igor Voks
-
Publication number: 20220398197Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.Type: ApplicationFiled: July 13, 2022Publication date: December 15, 2022Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks
-
Publication number: 20220283964Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.Type: ApplicationFiled: March 2, 2021Publication date: September 8, 2022Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
-
Patent number: 11397682Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.Type: GrantFiled: June 30, 2020Date of Patent: July 26, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks
-
Publication number: 20210406179Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.Type: ApplicationFiled: June 30, 2020Publication date: December 30, 2021Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks
-
Patent number: 10642775Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.Type: GrantFiled: June 30, 2019Date of Patent: May 5, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Igor Voks, Dror Bohrer, Lior Narkis, Ariel Shahar