Abstract: A fiber optic connector jack is provided with a backcap processing module. The jack includes a lens housing having a lensed lid. A connector flange extends from the lensed lid top surface, shaped to selectively engage a plug connector housing. A microlens having a first surface is formed in the lensed lid bottom surface. A convex surface is formed in the lensed lid top surface to transceive light in a collimated beam with a plug optical interface. A backcap enclosure wall extends from the lensed lid bottom surface. The jack also includes a backcap processing module with a circuit substrate and an optical element. The optical element (e.g., a laser diode or photodiode) has an optical interface formed in a focal plane of the microlens to transceive light with the microlens first surface. An electrical connector and electrical cable selectively engages a printed circuit board with the circuit substrate.

Abstract: Fiber optic cable jacks and plugs are provided. In one aspect, a cable is made from at least one length of fiber optic line having a first end and a second end. A first plug includes a one-piece mechanical body with a cable interface to engage the fiber optic line first end, and a microlens to transceive light with the cable interface. The first plug is shaped to engage a first jack housing. A second plug includes a one-piece mechanical body with a cable interface to engage the fiber optic line second end, and a microlens to transceive light with the cable interface. The second plug is shaped to engage a second jack housing. The mechanical bodies have inner walls that form an air gap cavity interposed between the microlens convex surface and an engaging jack optical interface.

Abstract: A Free Space Optics (FSO) connector is provided with a method for interfacing to an electronic circuit card electrical connector via the FSO connector. The method transceives electrical signals via an electronic circuit card electrical connector. Using an FSO connector, the method converts between electrical signals and optical signals, and transceives optical signals via free space. In one aspect, the optical signals are initially received via free space along a first axis, and reflected along a second axis. Further, the optical signals may be initially transmitted along the second axis and reflected into free space along the first axis. In another aspect, the optical signals are transceived in a plurality of directions in free space. For example, optical signals may be transmitted and received in four mutually-orthogonal axes.

Abstract: Methods, systems, and apparatuses related to a communication switch are disclosed herein. In some embodiments, the communication switch may be configured to transmit TDM, ATM and/or packet data from an ingress service processor, through a plurality of switch elements, to an egress service processor. Other embodiments may be described and claimed.

Abstract: Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.

Abstract: The location of a wireless handset is determined from a station such as another wireless handset in order, for example, to keep track of the current location of a child, friend or asset.

Abstract: Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.