Patents by Inventor Ih-Chin Chen
Ih-Chin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6960499Abstract: A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.Type: GrantFiled: June 14, 2004Date of Patent: November 1, 2005Assignee: Texas Instruments IncorporatedInventors: Mahalingam Nandakumar, Karthik Vasanth, Ih-Chin Chen
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Patent number: 6835622Abstract: Within a semiconductor fabrication and a method for fabricating the semiconductor fabrication there is provided a series of field effect devices having in a first instance an optional pair of different gate dielectric layer thicknesses, and in a second instance different dopant distribution profiles with respect to a pair of gate electrodes formed upon a pair of gate dielectric layers of a single thickness. The method provides the semiconductor fabrication with multiple gate dielectric layer thicknesses, actual and effective, with enhanced manufacturability and reliability.Type: GrantFiled: June 4, 2002Date of Patent: December 28, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Ling-Yen Yeh, Jyh-Chyurn Guo, Ih-Chin Chen
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Publication number: 20040224457Abstract: A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.Type: ApplicationFiled: June 14, 2004Publication date: November 11, 2004Inventors: Mahalingam Nandakumar, Karthik Vasanth, Ih-Chin Chen
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Publication number: 20030232473Abstract: Within a semiconductor fabrication and a method for fabricating the semiconductor fabrication there is provided a series of field effect devices having in a first instance an optional pair of different gate dielectric layer thicknesses, and in a second instance different dopant distribution profiles with respect to a pair of gate electrodes formed upon a pair of gate dielectric layers of a single thickness. The method provides the semiconductor fabrication with multiple gate dielectric layer thicknesses, actual and effective, with enhanced manufacturability and reliability.Type: ApplicationFiled: June 4, 2002Publication date: December 18, 2003Applicant: Taiwn Semiconductor Manufacturing Co., Ltd.Inventors: Ling-Yen Yeh, Jyh-Chyurn Guo, Ih-Chin Chen
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Patent number: 6420236Abstract: A system for producing metal gate MOSFETs having relatively low threshold voltages is disclosed, comprising the steps of forming 200 a gate oxide layer on a semiconductor substrate, forming 210 a dummy gate on the substrate, removing 260 the dummy gate after further processing and depositing 270 a lower metallic gate material on said gate oxide; treating 280 the semiconductor device with a reducing gas immediately after deposition of the lower metallic gate material, and depositing 290 an upper gate metal over the lower gate material.Type: GrantFiled: August 17, 2000Date of Patent: July 16, 2002Assignee: Texas Instruments IncorporatedInventors: Jerry C. Hu, Hong Yang, Amitava Chatterjee, Ih-Chin Chen
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Publication number: 20020076885Abstract: A method for forming a CMOS transistor with self-aligned cladding is provided that comprises forming a disposable gate structure (20) outwardly from a substrate (10) in a gate region (62) where the disposable gate structure (20) comprises a replaceable material (18). The method next provides for forming a source (40) and a drain (42) in the substrate (10) on opposite sides of the gate region (62). The method next provides for cladding the source region (40) and the drain region (42) using a self-aligned process. The method next provides for selectively removing the disposable gate structure (20), and forming a gate structure (70) in the gate region (62) vacated by the disposable gate structure (20). The method next provides for cladding a gate structure (70) using a self-aligned process.Type: ApplicationFiled: December 14, 2000Publication date: June 20, 2002Inventor: Ih-Chin Chen
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Publication number: 20010038131Abstract: A method for forming a ultra-shallow junction region (104). A silicon film (single crystalline, polycrystalline or amorphous) is deposited on the substrate (100) to form an elevated S/D (106). A metal film is deposited over the silicon film and reacted with the silicon film to form a silicide film (108). The silicon film is preferably completely consumed by the silicide film formation. An implant is performed to implant the desired dopant either into the metal film prior to silicide formation or into the silicide film after silicide formation. A high temperature anneal is used to drive the dopant out of the silicide film to form the junction regions (104) having a depth in the substrate (100) less than 200 Å. This high temperature anneal may be one of the anneals that are part of the silicide process or it may be an additional process step.Type: ApplicationFiled: January 14, 1999Publication date: November 8, 2001Inventors: JERRY CHE-JEN HU, QI-ZHONG HONG, STEVE HSIA, IH-CHIN CHEN
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Patent number: 6313010Abstract: A trench isolation structure including high density plasma enchanced silicon dioxide trench filling (122) with chemical mechanical polishing removal of non-trench oxide.Type: GrantFiled: June 9, 1997Date of Patent: November 6, 2001Assignee: Texas Instruments IncorporatedInventors: Somnath S. Nag, Amitava Chatterjee, Ih-Chin Chen
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Patent number: 6306724Abstract: A trench isolation structure can be formed in a stack trench capacitor fabrication process by forming a trench region (18) through a buffer layer (16) and an interface layer (12) and into a semiconductor substrate (14). A trench wall layer (20) is grown on inner walls of the trench region (18) and in contact with the interface layer (12). A trench filler layer (28) is formed on the buffer layer (16) and on the trench wall layer (20) within the trench region (18). The trench filler layer (28) is removed from the buffer layer (16) but remains within the trench region (18). A storage dielectric (30) is deposited on the buffer layer (16) and on the trench filler layer (28) within the trench region (18). A field plate layer (32) is deposited on the storage dielectric (30) and within the trench region (18). The field plate layer (32), the storage dielectric (30), the buffer layer (16), and the interface layer (12) lying outside the trench region (18) are removed.Type: GrantFiled: June 28, 1995Date of Patent: October 23, 2001Assignee: Texas Instruments IncorporatedInventor: Ih-Chin Chen
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Patent number: 6287924Abstract: Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.Type: GrantFiled: September 28, 1999Date of Patent: September 11, 2001Assignee: Texas Instruments IncorporatedInventors: Chih-Ping Chao, Ih-Chin Chen, Rick L. Wise, Katherine E. Violette, Sreenath Unnikrishnan
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Patent number: 6228725Abstract: A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).Type: GrantFiled: March 30, 1999Date of Patent: May 8, 2001Assignee: Texas Instruments IncorporatedInventors: Mahalingam Nandakumar, Amitava Chatterjee, Mark S. Rodder, Ih-Chin Chen
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Patent number: 6147384Abstract: A method of forming a field effect transistor with source and drain on an insulator includes forming a first void region (11) in the outer surface of a semiconductor body (10) and forming a second void region (11) in the outer surface of a semiconductor body. The first void region is separated from the second void region by a portion of the semiconductor body (10). The method further includes depositing a dielectric material in the first void region to form a first insulating region (16) and depositing a dielectric material in the second void region to form a second insulating region (16). The method further includes planarizing the first and second insulating regions to define a planar surface (17).Type: GrantFiled: August 17, 1999Date of Patent: November 14, 2000Assignee: Texas Instruments IncorporatedInventor: Ih-Chin Chen
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Patent number: 6143625Abstract: An isolation trench (60) may comprise a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A protective liner (50) may be formed over the barrier layer (22). The protective liner (50) may comprise a chemically deposited oxide. A high density layer of insulation material (55) may be formed in the trench (20) over the protective liner (50).Type: GrantFiled: September 10, 1998Date of Patent: November 7, 2000Assignee: Texas Instruments IncorporatedInventors: Ih-Chin Chen, Amitava Chatterjee, Somnath S. Nag
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Patent number: 5917219Abstract: A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').Type: GrantFiled: October 3, 1996Date of Patent: June 29, 1999Assignee: Texas Instruments IncorporatedInventors: Mahalingam Nandakumar, Amitava Chatterjee, Mark S. Rodder, Ih-Chin Chen
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Patent number: 5913135Abstract: A method for forming a transistor (50) includes forming a first insulating region (16) in the outer surface of a semiconductor body (10) and forming a second insulating region (16) in the outer surface of the semiconductor body (10) and spaced apart from the first insulating region by a region of semiconductor material. The method further includes planarizing the first and second insulating regions and the region of semiconductor material to define a planar surface (17) and forming a conductive source region (34) overlying the first insulating region. The method further includes forming a conductive drain region (36) overlying the second insulating region and forming a conductive gate body (24) overlying the planar surface (17) and spaced apart from the conductive source region (34) and the conductive drain region (36).A field effect transistor device (50) having a substrate (10) is provided.Type: GrantFiled: December 12, 1997Date of Patent: June 15, 1999Assignee: Texas Instruments IncorporatedInventor: Ih-Chin Chen
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Patent number: 5909628Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.Type: GrantFiled: February 21, 1997Date of Patent: June 1, 1999Assignee: Texas Instruments IncorporatedInventors: Amitava Chatterjee, Theodore W. Houston, Ih-Chin Chen, Agerico L. Esquirel, Somnath Nag, Iqbal Ali, Keith A. Joyner, Yin Hu, Jeffrey Alan McKee, Peter Stewart McAnally
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Patent number: 5894145Abstract: A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).Type: GrantFiled: August 12, 1997Date of Patent: April 13, 1999Assignee: Texas Instruments IncorporatedInventors: Ih-Chin Chen, Hisashi Shichijo, Clarence W. Teng
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Patent number: 5739569Abstract: A non-volatile memory cell structure capable of being programmed by band-to-band tunneling induced substrate hot electron injection is formed in a semiconductor substrate 8 and comprises first 10 and second 12 highly doped regions separated by a channel region 14. A nitride layer 16, such as silicon nitride for example, is formed over the channel region 14. An oxide layer 18, such as silicon dioxide, is then formed over nitride layer. The oxide/nitride layer serves as the floating gate insulator. In another embodiment, an additional oxide layer 15 may be formed between the channel region 14 and the nitride layer 16. The floating gate 20 is formed over the oxide layer 16 and a control gate 24 is insulatively formed over the floating gate 20. Other variations, advantages and a fabrication method are also disclosed.Type: GrantFiled: August 21, 1996Date of Patent: April 14, 1998Assignee: Texas Instruments IncorporatedInventor: Ih-Chin Chen
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Patent number: 5595925Abstract: A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).Type: GrantFiled: April 29, 1994Date of Patent: January 21, 1997Assignee: Texas Instruments IncorporatedInventors: Ih-Chin Chen, Hisashi Shichijo, Clarence W. Teng
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Patent number: 5548548Abstract: A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.Type: GrantFiled: December 19, 1994Date of Patent: August 20, 1996Assignee: Texas Instruments IncorporatedInventors: Amitava Chatterjee, Jiann Liu, Purnendu Mozumder, Mark S. Rodder, Ih-Chin Chen