Abstract: A nonvolatile semiconductor memory device capable of being changed in method of use according to its application and in addition having a high reliability and an IC memory card using the same. An IC memory card is provided with multi-level type flash memory chips and a controller as principal constituent elements and constituted so as to allow free selection of plurality of operation modes according to the application, that is, use where a storage capacity is large, but there is a reduction in the write/erase speed or the guaranteed number of the repeated rewrites or use where the storage capacity is small, but there is no reduction in the write/erase speed or the guaranteed number of the repeated rewrites.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: A nonvolatile semiconductor memory device capable of improving a reliability of a spare region, capable of improving the reliability of a data region in accordance with a method of use, and capable of realizing a function of an additional writing as a multi-level memory, and an IC memory card using the same, provided with a data region capable of storing 4-level and binary data; a spare region capable of storing binary data; data region use decoders for supplying a drive voltage to the data region; spare region use decoders and for supplying the drive voltage to the spare region; a latch circuit for transferring data with the data region in accordance with the number of levels of the multi-level data to be stored in the data region and stopping the supply of the drive voltage of the sub decoder when the transfer of data is normally completed; and a latch circuit for transferring data with the spare region and stopping the supply of the drive voltage of the sub decoder when the transfer of data is normally com

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: A ferroelectric nonvolatile semiconductor memory using a ferroelectric film as a dielectric film between a floating gate and a control gate, wherein a write switching transistor is provided between the floating gate and the bit line so as to enable the application of any voltage to the ferroelectric film using the voltage applied to the control gate and the voltage applied to the bit line and thereby enabling writing by a low voltage.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film. In which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: An SRAM cell comprising a flip-flop consisting of first and second inverters, and two word transistors connected to the flip-flop. In this cell, the gates of the word transistors are composed of a single word line, and the gate of a driver transistor in the first inverter is provided on one side of the word line, while the gate of a driver transistor in the second inverter is provided on the other side of the word line. The gate regions of the driver transistors in the first and second inverters are so formed as to partially overlap the bit-line side diffused layer regions of the word transistors. Also disclosed is a memory cell array comprising a plurality of cell rows each having a plurality of the above SRAM cells. In this array, the memory cells disposed in the even row are so arranged as to have a positional deviation of approximately half the cell length in the same direction respectively from the memory cells disposed in the odd row.

Abstract: An SRAM cell comprising a flip-flop consisting of first and second inverters, and two word transistors connected to the flip-flop. In this cell, the gates of the word transistors are composed of a single word line, and the gate of a driver transistor in the first inverter is provided on one side of the word line, while the gate of a driver transistor in the second inverter is provided on the other side of the word line. The gate regions of the driver transistors in the first and second inverters are so formed as to partially overlap the bit-line side diffused layer regions of the word transistors. Also disclosed is a memory cell array comprising a plurality of cell rows each having a plurality of the above SRAM cells. In this array, the memory cells disposed in the even row are so arranged as to have a positional deviation of approximately half the cell length in the same direction respectively from the memory cells disposed in the odd row.