Patents by Inventor Ihor Brunets
Ihor Brunets has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10825900Abstract: A semiconductor switch device and a method of making the same. The device includes a semiconductor substrate having a major surface. The device also includes a first semiconductor region located in the substrate beneath the major surface. The device includes an elongate gate located on the major surface. The device also includes a source region and a drain region located in the first semiconductor region adjacent respective first and second elongate edges of the gate. The device also includes electrical contacts for the source and drain regions. The contacts include at least two contacts located on either the source region or the drain region, which are spaced apart along a direction substantially parallel the elongate edges of the gate. The device further includes an isolation region located between the at least two contacts. The isolation region extends through the source/drain region from the major surface to the first semiconductor region.Type: GrantFiled: June 7, 2018Date of Patent: November 3, 2020Assignee: NXP B.V.Inventors: Mahmoud Shehab Mohammad Al-Sa'di, Petrus Hubertus Cornelis Magnee, Ihor Brunets, Jan Willem Slotboom, Tony Vanhoucke
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Patent number: 10566423Abstract: A semiconductor switch device for switching an RF signal and a method of making the same. The device includes a first semiconductor region having a first conductivity type. The device also includes a source region and a drain region located in the first semiconductor region. The source region and the drain region have a second conductivity type. The second conductivity type is different to the first conductivity type. The device further includes a gate separating the source region from the drain region. The device also includes at least one sinker region having the second conductivity type. Each sinker region is connectable to an external potential for drawing minority carriers away from the source and drain regions to reduce a leakage current at junctions between the source and drain regions and the first semiconductor region.Type: GrantFiled: December 31, 2016Date of Patent: February 18, 2020Assignee: NXP B.V..Inventors: Mahmoud Shehab Mohammad Al-Sa'di, Johannes Josephus Theodorus Marinus Donkers, Petrus Hubertus Cornelis Magnee, Ihor Brunets, Anurag Vohra, Jan Willem Slotboom
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Publication number: 20190019867Abstract: A semiconductor switch device and a method of making the same. The device includes a semiconductor substrate having a major surface. The device also includes a first semiconductor region located in the substrate beneath the major surface. The device includes an elongate gate located on the major surface. The device also includes a source region and a drain region located in the first semiconductor region adjacent respective first and second elongate edges of the gate. The device also includes electrical contacts for the source and drain regions. The contacts include at least two contacts located on either the source region or the drain region, which are spaced apart along a direction substantially parallel the elongate edges of the gate. The device further includes an isolation region located between the at least two contacts. The isolation region extends through the source/drain region from the major surface to the first semiconductor region.Type: ApplicationFiled: June 7, 2018Publication date: January 17, 2019Inventors: Mahmoud Shehab Mohammad Al-Sa'di, Petrus Hubertus Cornelis Magnee, Ihor Brunets, Jan Willem Slotboom, Tony Vanhoucke
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Patent number: 10158002Abstract: A method of making a semiconductor switch device and a semiconductor switch device made according to the method. The method includes depositing a gate dielectric on a major surface of a substrate. The method also includes depositing and patterning a gate electrode on the gate dielectric. The method further includes depositing an oxide to cover the top surface and sidewall(s) of the gate electrode. The method also includes, after depositing the oxide, performing a first ion implantation process at a first implantation dosage for forming a lightly doped drain region of the switch device. The method further includes forming sidewall spacers on the sidewall(s) of the gate electrode. The method also includes performing a second ion implantation process at a second implantation dosage for forming a source region and a drain region of the semiconductor switch device. The second implantation dosage is greater than the first implantation dosage.Type: GrantFiled: August 15, 2017Date of Patent: December 18, 2018Assignee: NXP B.V.Inventors: Mahmoud Al-sa'di, Petrus Magnee, Johannes Donkers, Ihor Brunets, Joost Melai
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Publication number: 20180053833Abstract: A method of making a semiconductor switch device and a semiconductor switch device made according to the method. The method includes depositing a gate dielectric on a major surface of a substrate. The method also includes depositing and patterning a gate electrode on the gate dielectric. The method further includes depositing an oxide to cover the top surface and sidewall(s) of the gate electrode. The method also includes, after depositing the oxide, performing a first ion implantation process at a first implantation dosage for forming a lightly doped drain region of the switch device. The method further includes forming sidewall spacers on the sidewall(s) of the gate electrode. The method also includes performing a second ion implantation process at a second implantation dosage for forming a source region and a drain region of the semiconductor switch device. The second implantation dosage is greater than the first implantation dosage.Type: ApplicationFiled: August 15, 2017Publication date: February 22, 2018Inventors: Mahmoud Al-sa'di, Petrus Magnee, Johannes Donkers, Ihor Brunets, Joost Melai
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Publication number: 20170221994Abstract: A semiconductor switch device for switching an RF signal and a method of making the same. The device includes a first semiconductor region having a first conductivity type. The device also includes a source region and a drain region located in the first semiconductor region. The source region and the drain region have a second conductivity type. The second conductivity type is different to the first conductivity type. The device further includes a gate separating the source region from the drain region. The device also includes at least one sinker region having the second conductivity type. Each sinker region is connectable to an external potential for drawing minority carriers away from the source and drain regions to reduce a leakage current at junctions between the source and drain regions and the first semiconductor region.Type: ApplicationFiled: December 31, 2016Publication date: August 3, 2017Inventors: Mahmoud Shehab Mohammad Al-Sa'di, Johannes Josephus Theodorus Marinus Donkers, Petrus Hubertus Cornelis Magnee, Ihor Brunets, Anurag Vohra, Jan Willem Slotboom
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Patent number: 8848194Abstract: An integrated plasmonic sensing device is described wherein the integrated device comprises: at least one optical source comprising a first conductive layer and a second conductive layer, and a optical active layer between at least part of said first and second conductive layers; at least one nanocavity extending through said first and second conductive layers and said optical active layer, wherein said optical source is configured to generate surface plasmon modes suitable for optically activating one or more resonances in said nanocavity; and, at least one optical detector comprising at least one detection region formed in said substrate in the vicinity of said nanocavity resonator, wherein said optical detector is configured to sense optically activated resonances in said nanocavity.Type: GrantFiled: April 6, 2011Date of Patent: September 30, 2014Assignee: Integrated Plasmonics CorporationInventors: Robert Walters, Jurriaan Schmitz, Albert Polman, Ihor Brunets
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Publication number: 20130148126Abstract: An integrated plasmonic sensing device is described wherein the integrated device comprises: at least one optical source comprising a first conductive layer and a second conductive layer, and a optical active layer between at least part of said first and second conductive layers; at least one nanocavity extending through said first and second conductive layers and said optical active layer, wherein said optical source is configured to generate surface plasmon modes suitable for optically activating one or more resonances in said nanocavity; and, at least one optical detector comprising at least one detection region formed in said substrate in the vicinity of said nanocavity resonator, wherein said optical detector is configured to sense optically activated resonances in said nanocavity.Type: ApplicationFiled: April 6, 2011Publication date: June 13, 2013Applicant: Integrated Plasmonics CorporationInventors: Robert Walters, Jurriaan Schmitz, Albert Polman, Ihor Brunets