Patents by Inventor Ihsan J. Djomehri

Ihsan J. Djomehri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of growing as a channel region to reduce source/drain junction capacitance
    Patent number: 6955969
    Abstract: A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: October 18, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ihsan J. Djomehri, Jung-Suk Goo, Srinath Krishnan, Witold P. Maszara, James N. Pan, Qi Xiang
  • Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift
    Patent number: 6929992
    Abstract: The threshold voltage shift exhibited by strained silicon NMOS devices is compensated with respect to the threshold voltages of PMOS devices formed on the same substrate by increasing the work function of the NMOS gates. The NMOS gate work function exceeds the PMOS gate work function so as to compensate for a difference in the respective NMOS and PMOS threshold voltages. The NMOS gates are preferably fully silicided while the PMOS gates are partially silicided.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: August 16, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ihsan J. Djomehri, Qi Xiang, Jung-Suk Goo, James N. Pan