Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: In various embodiments, a three-dimensional structured nonvolatile semiconductor memory devices and methods for manufacturing the devices are disclosed. One such device includes an n-type doped region at a source/drain region; a p-type doped region at the source/drain region; and a diffusion barrier material between the n-type doped region and the p-type doped region. The n-type doped region is substantially isolated from the p-type doped region. Other embodiments are also disclosed.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A non-volatile memory device includes a plurality of select lines and a plurality of word lines formed over a semiconductor substrate, a contact plug formed between the select lines, and a conductive interference shielding line formed between the select line and a word line adjacent to the select line and isolated from the semiconductor substrate.

Abstract: A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.