Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips.

Abstract: A dielectric structure is formed by a molding process, so that a first surface of a dielectric structure is shaped by contact with the mold. The opposite second surface of the dielectric structure is applied onto the front surface of a wafer element. The dielectric layer may include protruding bumps and terminals may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts which extend above a surrounding solder mask layer to facilitate engagement with a test fixture. The posts are immersed within solder joints when the structure is bonded to a circuit panel.

Abstract: A microelectronic assembly includes a microelectronic package having a microelectronic element with faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The package includes a plurality of support elements disposed between the microelectronic element and the substrate and supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements. The assembly includes a circuitized substrate having conductive pads confronting the conductive posts of the microelectronic package, whereby the conductive posts are electrically interconnected with the conductive pads.