Patents by Inventor Ik Joon CHOI
Ik Joon CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240057324Abstract: A semiconductor memory device includes n physical banks, each of which is configured to be entirely or partially included in one of a first logic bank or a second logic bank and arranged in a row direction, wherein n is an integer that is greater than or equal to 3, and wherein a proportion of a sum of respective widths of the n physical banks in the row direction to a height of the n physical banks in a column direction is a real number multiple that is not a multiple of 2.Type: ApplicationFiled: May 5, 2023Publication date: February 15, 2024Inventors: Ik-Joon Choi, Kihyun Kim, Sungchul Park, Minjun Kim, Junhyung Kim
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Patent number: 11114139Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: GrantFiled: February 10, 2021Date of Patent: September 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Publication number: 20210166740Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: ApplicationFiled: February 10, 2021Publication date: June 3, 2021Inventors: Hyun-Sung SHIN, Ik-Joon CHOI, So-Young KIM, Tae-Kyu BYUN, Jae-Youn YOUN
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Patent number: 10957380Abstract: According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.Type: GrantFiled: March 29, 2019Date of Patent: March 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-sung Shin, Dae-Jeong Kim, Ik-Joon Choi
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Patent number: 10923165Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: GrantFiled: January 15, 2020Date of Patent: February 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Publication number: 20200152244Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Patent number: 10553260Abstract: A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: GrantFiled: July 18, 2018Date of Patent: February 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Publication number: 20200027497Abstract: According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects the a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.Type: ApplicationFiled: March 29, 2019Publication date: January 23, 2020Inventors: Hyun-sung SHIN, Dae-Jeong KIM, Ik-Joon CHOI
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Patent number: 10497422Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.Type: GrantFiled: January 12, 2018Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-jun Lee, Seung-jun Shin, Hoon Sin, Ik-joon Choi, Ju-seong Hwang
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Publication number: 20190192701Abstract: Provided are a conjugate including an EGFR inhibitor that enables treatment and diagnosis of epidermal growth factor receptor (EGFR)-overexpressing tumors including resistant tumors, a method that enables drug delivery treatment and diagnosis of EGFR-overexpressing tumors using the conjugate, and a method of preparing the conjugate.Type: ApplicationFiled: December 26, 2018Publication date: June 27, 2019Applicant: Korea Institute of Radiological & Medical SciencesInventors: Tae Sup Lee, Ik Joon Choi, Joo Hyun Kang
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Publication number: 20190096453Abstract: A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: ApplicationFiled: July 18, 2018Publication date: March 28, 2019Inventors: HYUN-SUNG SHIN, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Publication number: 20180342283Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.Type: ApplicationFiled: January 12, 2018Publication date: November 29, 2018Inventors: Seung-jun LEE, Seung-jun SHIN, Hoon SIN, Ik-joon CHOI, Ju-seong HWANG
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Publication number: 20090141009Abstract: Provided are a liquid crystal display (LCD) driver integrated circuit (IC) and a method for manufacturing the same. The LCD driver IC comprises a conductor, a first passivation layer, a first bump, and a first lead. The conductor is disposed on a source driver. The first passivation is disposed on the conductor and comprises a first trench exposing an upper side of the conductor. The first bump fills the first trench. The first lead is disposed on the first bump.Type: ApplicationFiled: July 11, 2008Publication date: June 4, 2009Inventors: Ik Joon CHOI, Jong Kee Kim