Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks, each block having a plurality of pages, each page having a plurality of memory cells, wherein the plurality of memory block includes an SLC (Single Level Cell) block and an MLC (Multi-Level Cell) block; and a controller suitable for programming input data transmitted from a host to both the SLC block and the MLC block in response to a first program command, and invalidating the input data programmed in the SLC block at a time point when the program operation for the MLC block is completed, when the memory system is powered on after an SPO (Sudden Power-Off) occurred while the program operation was performed on both the SLC block and the MLC block, the controller may perform a recovery operation to the MLC block based on valid data programmed in the SLC block.

Abstract: A controller for controlling a non-volatile memory apparatus including page groups each including a plurality of pages is configured to select a target page group from the page groups, wherein the target page group includes at least one invalid page and at least one valid page, select, as a target threshold voltage distribution, a lower threshold voltage distribution of two adjacent threshold voltage distributions distinguished by an invalid read voltage, wherein the invalid read voltage is a read voltage for distinguishing between data stored in the invalid page, select, as a target memory cell, a memory cell located in the target threshold voltage distribution among a plurality of memory cells configuring the target page group, and control the non-volatile memory apparatus to perform an adjustment program operation for raising a threshold voltage of the target memory cell as much as a first voltage.

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks, each block having a plurality of pages, each page having a plurality of memory cells, wherein the plurality of memory block includes an SLC (Single Level Cell) block and an MLC (Multi-Level Cell) block; and a controller suitable for programming input data transmitted from a host to both the SLC block and the MLC block in response to a first program command, and invalidating the input data programmed in the SLC block at a time point when the program operation for the MLC block is completed, when the memory system is powered on after an SPO (Sudden Power-Off) occurred while the program operation was performed on both the SLC block and the MLC block, the controller may perform a recovery operation to the MLC block based on valid data programmed in the SLC block.

Abstract: A controller for controlling a non-volatile memory apparatus including page groups each including a plurality of pages is configured to select a target page group from the page groups, wherein the target page group includes at least one invalid page and at least one valid page, select, as a target threshold voltage distribution, a lower threshold voltage distribution of two adjacent threshold voltage distributions distinguished by an invalid read voltage, wherein the invalid read voltage is a read voltage for distinguishing between data stored in the invalid page, select, as a target memory cell, a memory cell located in the target threshold voltage distribution among a plurality of memory cells configuring the target page group, and control the non-volatile memory apparatus to perform an adjustment program operation for raising a threshold voltage of the target memory cell as much as a first voltage.

Abstract: A method for operating a data storage device including memory regions each including memory units of levels, the levels respectively corresponding to bitmaps, and each of the bitmaps including entries respectively corresponding to the memory regions includes controlling a read operation for a first memory unit of a first level among the levels in a first memory region among the memory regions; increasing a read count by checking a first entry corresponding to the first memory region in a first bit map corresponding to the first level, wherein each of entries included in the first bitmap reflects whether a corresponding memory region is included in at least one second memory region in which a memory unit of the first level has been read, during a predetermined period before the read operation for the first memory unit; and performing a management operation for the memory regions, based on the read count.

Abstract: A memory system and an operating method thereof are disclosed. A memory system includes a memory device configured to correct first data read from a first data storage region based on error correction data thereby generating second data and store the second data in a second data storage region; and a controller configured to generate the error correction data. The error correction data includes location information of an error bit of the first data.

Abstract: The technology disclosed in this patent document can be implemented in embodiments to provide a memory system capable of improving a read operation, using an error correction technique (e.g., chipkill) that recovers data in correcting a data failure including a multibit failure, and an operation method of the memory system. The disclosed read operations based on recovery can be used for retrieving data from a memory chip by reconstructing the same data from other memory chips without accessing the memory chip and can be applied in various memory systems.

Abstract: A memory control having improved cache program operation performance controls a memory device. The memory controller includes: a command queue for sequentially storing commands to be executed by the memory device; a cache program determinerfor determining, when a first command that is a program command stored in the command queue is provided to the memory device, whether a second command to be executed next in time to the first command is a program command; and a program operation controller for controlling the memory device to perform a program operation according to the first command as a normal program operation or cache program operation, depending on whether the second command is a program command.

Abstract: Provided herein is a memory system and a method for driving the memory system. The memory system may include: a semiconductor memory device including a plurality of memory blocks and a block information storing block; and a controller configured to control the semiconductor memory device to store block information about the memory blocks into the block information storing block during an overall operation of the semiconductor memory device, and perform, during a power loss recovery operation, a recovery operation using the block information stored in the block information storing block.

Abstract: The technology disclosed in this patent document can be implemented in embodiments to provide a memory system capable of improving a read operation, using an error correction technique (e.g., chipkill) that recovers data in correcting a data failure including a multibit failure, and an operation method of the memory system. The disclosed read operations based on recovery can be used for retrieving data from a memory chip by reconstructing the same data from other memory chips without accessing the memory chip and can be applied in various memory systems.

Abstract: A data storage device includes a nonvolatile memory device including a memory block having a plurality of memory regions; and a controller suitable for searching a first memory region for which error correction is passed, by scanning the plurality of memory regions in a reverse order of a write sequence for the memory block, determining a target memory region in the memory block based on data stored in the first memory region, and performing a recovery operation for the target memory region.

Abstract: A method for operating a data storage device including memory regions each including memory units of levels, the levels respectively corresponding to bitmaps, and each of the bitmaps including entries respectively corresponding to the memory regions includes controlling a read operation for a first memory unit of a first level among the levels in a first memory region among the memory regions; increasing a read count by checking a first entry corresponding to the first memory region in a first bit map corresponding to the first level, wherein each of entries included in the first bitmap reflects whether a corresponding memory region is included in at least one second memory region in which a memory unit of the first level has been read, during a predetermined period before the read operation for the first memory unit; and performing a management operation for the memory regions, based on the read count.

Abstract: A data storage device may include a plurality of nonvolatile memory devices including a plurality of blocks and a controller suitable for generating super block parity data for a super block, which is formed of one or more of the plurality of blocks.

Abstract: A method for operating a data storage device including a plurality of memory regions. The method includes performing a read operation for a first memory region, increasing a read count based on read sequences of the first memory region and a second memory region which has been read before the read operation for the first memory region, and performing a management operation for the plurality of memory regions based on the read count.

Abstract: A data storage device includes a nonvolatile memory device including a memory block having a plurality of memory regions; and a controller suitable for searching a first memory region for which error correction is passed, by scanning the plurality of memory regions in a reverse order of a write sequence for the memory block, determining a target memory region in the memory block based on data stored in the first memory region, and performing a recovery operation for the target memory region.

Abstract: A method for operating a data storage device including a plurality of memory regions. The method includes performing a read operation for a first memory region, increasing a read count based on read sequences of the first memory region and a second memory region which has been read before the read operation for the first memory region, and performing a management operation for the plurality of memory regions based on the read count.

Abstract: A data storage device may include a plurality of nonvolatile memory devices including a plurality of blocks and a controller suitable for generating super block parity data for a super block, which is formed of one or more of the plurality of blocks.

Abstract: The present invention relates to a grouping method and device for enhancing redundancy removing performance for a storage unit such as a hard disk, a solid state disk (SSD), etc. The grouping method for enhancing performance of a redundancy removing technology may include: extracting samples from data that is stored in a buffer of a memory and is standing by to be processed; performing remaining calculations on the extracted samples; and grouping samples by connecting them to a bucket corresponding to a resultant value of the remaining calculations.

Abstract: The present invention relates to a grouping method and device for enhancing redundancy removing performance for a storage unit such as a hard disk, a solid state disk (SSD), etc. The grouping method for enhancing performance of a redundancy removing technology may include: extracting samples from data that is stored in a buffer of a memory and is standing by to be processed; performing remaining calculations on the extracted samples; and grouping samples by connecting them to a bucket corresponding to a resultant value of the remaining calculations.