Abstract: In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern.

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Abstract: In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern.

Abstract: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

Abstract: A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a conductive layer until the conductive layer fills the contact holes; removing surface roughness created during the formation of the conductive layer by a first etch-back process; and planarizing the conductive layer by a second etch-back process until the gate hard mask is exposed.

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Abstract: A method for fabricating a semiconductor device includes forming a fuse line over a first region of a substrate, forming a first insulation layer over the fuse line and the substrate, forming a capacitor including an electrode over a second region of the substrate, such that a conductive layer for the electrode is patterned over the first insulation layer of the first region to overlap with the fuse line, forming a second insulation layer over the capacitor, etching the second insulation layer using the patterned conductive layer of the first region as an etch stop layer, and etching the patterned conductive layer and the first insulation layer to make a portion of the first insulation layer remain over the fuse line at a certain thickness.

Abstract: Disclosed is a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC etching process and a defect generation during performing a plug isolation process. The present invention prevents a Pinocchio defect that is a fundamental problem caused by the chemical mechanical polishing (CMP) process and simplifies a subsequent cleaning process performed according to the particles. Accordingly, it is possible to develop products with a high quality and a high speed and to replace the CMP process having a high unit process cost with an etch back process, thereby providing an effect of increasing a price competitiveness.

Abstract: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

Abstract: A method for forming a metal line in a semiconductor device includes forming a plug buried in an inter-layer insulation layer formed over a substrate, forming a metal line layer over the plug and the substrate, forming a contact mask over the metal line layer, etching first portions of the metal line layer using the contact mask as an etch mask to form openings, forming a spacer layer over the metal line layer and the contact mask, and etching second portions of the metal line layer underneath the openings until portions of the inter-layer insulation layer are exposed to form spacers on sidewalls of the first portions of the metal line layer and the contact mask and to obtain isolated metal lines.

Abstract: A method for forming a contact hole in a semiconductor device includes preparing a substrate including a bottom structure; forming an insulation layer such that the insulation layer covers the bottom structure; forming a silicon-rich oxynitride layer on the insulation layer; forming a photoresist pattern on the silicon-rich oxynitride layer; etching the silicon-rich oxynitride layer using the photoresist pattern as an etch mask, thereby obtaining hard masks; and etching the insulation layer using the photoresist pattern and the hard masks as an etch mask to form a contact hole exposing a portion of the bottom structure.

Abstract: The present invention provides a method of fabricating a capacitor for a semiconductor device. The method includes: forming sequentially a lower electrode and a dielectric layer having a high dielectric constant over a semiconductor substrate which have gone through predetermined processes; forming sequentially a first metal layer and a poly-silicon layer over the dielectric layer; forming an upper electrode pattern by pattering the poly-silicon layer and the first metal layer; forming a second metal layer covering the upper electrode pattern on an entire surface of the semiconductor substrate; and forming an upper electrode constituted with the second metal layer, the poly-silicon layer and the first metal layer by patterning the second metal layer so that the second metal layer is connected with the first metal layer.

Abstract: A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a conductive layer until the conductive layer fills the contact holes; removing surface roughness created during the formation of the conductive layer by a first etch-back process; and planarizing the conductive layer by a second etch-back process until the gate hard mask is exposed.

Abstract: Disclosed is a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC etching process and a defect generation during performing a plug isolation process. The present invention prevents a Pinocchio defect that is a fundamental problem caused by the chemical mechanical polishing (CMP) process and simplifies a subsequent cleaning process performed according to the particles. Accordingly, it is possible to develop products with a high quality and a high speed and to replace the CMP process having a high unit process cost with an etch back process, thereby providing an effect of increasing a price competitiveness.

Abstract: The present invention provides a method of fabricating a capacitor for a semiconductor device. The method includes: forming sequentially a lower electrode and a dielectric layer having a high dielectric constant over a semiconductor substrate which have gone through predetermined processes; forming sequentially a first metal layer and a poly-silicon layer over the dielectric layer; forming an upper electrode pattern by pattering the poly-silicon layer and the first metal layer; forming a second metal layer covering the upper electrode pattern on an entire surface of the semiconductor substrate; and forming an upper electrode constituted with the second metal layer, the poly-silicon layer and the first metal layer by patterning the second metal layer so that the second metal layer is connected with the first metal layer.

Abstract: A method for fabricating a resistive load static random access memory (SRAM) capable of providing a high resistive load without local resistance variation, includes a step of forming an isolated layer on a semiconductor substrate having driver and access transistors provided thereto, a step of selectively etching said isolated layer to provide a butting contact region, a step of forming a doped polysilicon layer on a resulting structure, a step of selectively counter-doping said doped polysilicon layer, and a step of patterning said doped polysilicon layer to provide a power supply line, a butting contact and a high load resistor.

Abstract: An improved method for forming a capacitor which is capable of increasing cell capacitance is disclosed. The capacitor easily formed a sequential two-step etching processes. The two-step etching include a selectively etching to form the contact hole for exposing an etch stop layer between gate electrodes, and an isotopically dry etching to maximize capacitor surface area without cleaning process after the selectively etching, an interlayer insulating layer being patterned in a manner which produces inner interlayer contact sidewalls having standing wave ripples and removes the exposed etch stop layer. As a result, it is found that the capacitor which is obtained by a simple and easy two-step dry etching exhibits an increased capacitor surface area. Furthermore, it is possible to form the stacked capacitor having sufficiently high storage capacitance without increasing the contact resistance.

Abstract: A method of controlling an excavator driven by an electronic control system having an input/output board for executing a transformation, scaling and filtering function of signals supplied from a hydraulic control portion, a central processing unit for storing the data output of the input/output board into a specified area of a RAM and transferring the data stored in the RAM to a ROM and a multi-control valve for distributing the data in the RAM to each of control parts in the hydraulic control portion as control signals, comprises a step of arranging the data inputted through the input/output board into a data area A for a plurality of tasks 1 and 2, a step of processing the data in the data area A by using executive codes for the plurality of tasks 1 (B) and task 2 (C), a step of executing the tasks in correlation with a system library D after the data area processing step, and a step of transferring control signals to the control parts in the hydraulic control portion through an input/output driver and the