Patents by Inventor Ikio Sugiura

Ikio Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9953844
    Abstract: When a plating layer is formed on through holes in semiconductor packages, first and second stacked bodies are stacked with first and second cavities formed in the first and second stacked bodies facing the inner side and are bonded together by applying adhesive to peripheral regions so that the cavities of the first and second stacked bodies form sealed spaces, and the through holes are formed such that part of the first and second stacked bodies including the bonding surface remains. Then, the through holes are plated to form the plating layer, the peripheral regions are removed as cutting allowances, i.e., removal regions, and the first and second stacked bodies are divided into a plurality of pieces along dicing lines to form semiconductor packages.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: April 24, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masanori Nimura, Shigenori Takeda, Yoshinao Tatei, Ikio Sugiura
  • Publication number: 20160163565
    Abstract: When a plating layer is formed on through holes in semiconductor packages, first and second stacked bodies are stacked with first and second cavities formed in the first and second stacked bodies facing the inner side and are bonded together by applying adhesive to peripheral regions so that the cavities of the first and second stacked bodies form sealed spaces, and the through holes are formed such that part of the first and second stacked bodies including the bonding surface remains. Then, the through holes are plated to form the plating layer, the peripheral regions are removed as cutting allowances, i.e., removal regions, and the first and second stacked bodies are divided into a plurality of pieces along dicing lines to form semiconductor packages.
    Type: Application
    Filed: June 9, 2014
    Publication date: June 9, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masanori NIMURA, Shigenori TAKEDA, Yoshinao TATEI, Ikio SUGIURA
  • Publication number: 20120091572
    Abstract: The semiconductor package includes a package wiring board having an element housing recessed portion on its top surface to house a semiconductor element; multiple side electrodes which are arranged on the outer side surface of the package wiring board and soldered to multiple motherboard electrodes arranged on a motherboard; a semiconductor element fixed onto the bottom surface of the element housing recessed portion; and an element electrode arranged on the bottom of the element housing recessed portion and electrically connected to the semiconductor element and the side electrodes. The package wiring board has a multilayered structure in which woven fabric and a resin adhesive layer are alternately laminated, and the resin adhesive layer is formed of a resin adhesive that contains inorganic filler particles.
    Type: Application
    Filed: June 22, 2009
    Publication date: April 19, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Hamaguchi, Ikio Sugiura, Hiroo Sakamoto, Masaki Iwata, Takashi Shirase, Takashi Okamuro