Abstract: This invention addresses difficult issues encountered in simulations and design verification efforts on complex microprocessor/digital signal processor devices. The invention provides a means for monitoring and tracking pending bugs and automates the rejection of already known/pending bugs. This allows developers/debuggers to focus on finding and correcting new bugs. This improves design development efficiency many fold and lets design engineers and verification engineers focus on real, new and unique issues. This is especially true when test cases are generated in a random way and the test case contents are actually unknown.