Patents by Inventor Iksoo Pyo

Iksoo Pyo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for routing using deferred merging
    Patent number: 6766502
    Abstract: A deferred merging router. Partial feasible routing solutions corresponding to each of a subset of a set of wires to be routed are identified. The partial feasible routing solutions are then merged to identify one or more feasible routing solutions for the set of wires to be routed. In one aspect of the invention, the final routing for an integrated circuit device may then be selected from the feasible routing solutions which may be ordered by one or more user-selected cost functions.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: July 20, 2004
    Assignee: Intel Corporation
    Inventors: Iksoo Pyo, Michelle Yu
  • Method and system for dynamically generating resistance, capacitance, and delay table look-ups
    Patent number: 6658631
    Abstract: A method and system for generating resistance, capacitance and delay table look-ups for cell routers and placers is disclosed. The system receives statistical data describing a new net as well as a desired level of accuracy. One or more preexisting net models are divided into one or more groups, wherein the number of groups is associated with the desired level of accuracy. The system returns a table of coefficients associated with the statistical data and the one or more groups.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: December 2, 2003
    Assignee: Intel Corporation
    Inventors: Iksoo Pyo, Artour Levin