Patents by Inventor Ikue Mitsuhashi

Ikue Mitsuhashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200105814
    Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 2, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hideto HASHIGUCHI, Reijiroh SHOHJI, Hiroshi HORIKOSHI, Ikue MITSUHASHI, Tadashi IIJIMA, Takatoshi KAMESHIMA, Minoru ISHIDA, Masaki HANEDA
  • Publication number: 20200105813
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 2, 2020
    Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
  • Publication number: 20200098815
    Abstract: [Object] To further improve performance of a solid-state imaging device.
    Type: Application
    Filed: March 23, 2018
    Publication date: March 26, 2020
    Inventors: TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, HIROSHI HORIKOSHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, MASAKI HANEDA
  • Publication number: 20200091217
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.
    Type: Application
    Filed: March 23, 2018
    Publication date: March 19, 2020
    Inventors: HIROSHI HORIKOSHI, MINORU ISHIDA, REIJIROH SHOHJI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, MASAKI HANEDA
  • Patent number: 10249674
    Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 2, 2019
    Assignee: Sony Corporation
    Inventors: Ikue Mitsuhashi, Kentaro Akiyama, Koji Kikuchi
  • Publication number: 20180286911
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Applicant: Sony Corporation
    Inventors: Yoshihisa KAGAWA, Nobutoshi FUJII, Masanaga FUKASAWA, Tokihisa KANEGUCHI, Yoshiya HAGIMOTO, Kenichi AOYAGI, Ikue MITSUHASHI
  • Patent number: 10026769
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 17, 2018
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
  • Publication number: 20170338268
    Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.
    Type: Application
    Filed: December 6, 2016
    Publication date: November 23, 2017
    Inventors: Ikue Mitsuhashi, Kentaro Akiyama, Koji Kikuchi
  • Patent number: 9627429
    Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: April 18, 2017
    Assignee: Sony Corporation
    Inventors: Ikue Mitsuhashi, Kentaro Akiyama, Koji Kikuchi
  • Patent number: 9525004
    Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: December 20, 2016
    Assignee: Sony Corporation
    Inventors: Ikue Mitsuhashi, Kentaro Akiyama, Koji Kikuchi
  • Publication number: 20160233264
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Application
    Filed: September 19, 2014
    Publication date: August 11, 2016
    Applicant: SONY CORPORATION
    Inventors: Yoshihisa KAGAWA, Nobutoshi FUJII, Masanaga FUKASAWA, Tokihisa KANEGUCHI, Yoshiya HAGIMOTO, Kenichi AOYAGI, Ikue MITSUHASHI
  • Publication number: 20160218137
    Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.
    Type: Application
    Filed: March 31, 2016
    Publication date: July 28, 2016
    Inventors: Ikue Mitsuhashi, Kentaro Akiyama, Koji Kikuchi
  • Publication number: 20150372041
    Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Inventors: Ikue Mitsuhashi, Kentaro Akiyama, Koji Kikuchi
  • Patent number: 9153490
    Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: October 6, 2015
    Assignee: SONY CORPORATION
    Inventors: Ikue Mitsuhashi, Kentaro Akiyama, Koji Kikuchi
  • Patent number: 9093348
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first circuit substrate having a first interconnection; forming a second circuit substrate having a second interconnection; bonding the first circuit substrate to the top surface of the second circuit substrate so as to be stacked facing each other; and performing an etching process of simultaneously removing parts formed on the first interconnection and the second interconnection in a stacked body of the first circuit substrate and the second circuit substrate so as to form a first opening in the top surface of the first interconnection and to form a second opening in the top surface of the second interconnection. The forming of the first circuit substrate includes forming an etching stopper layer on the surface of the first interconnection out of a material having an etching rate lower than that of the first interconnection in the etching process.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 28, 2015
    Assignee: SONY CORPORATION
    Inventor: Ikue Mitsuhashi
  • Publication number: 20140231950
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first circuit substrate having a first interconnection; forming a second circuit substrate having a second interconnection; bonding the first circuit substrate to the top surface of the second circuit substrate so as to be stacked facing each other; and performing an etching process of simultaneously removing parts formed on the first interconnection and the second interconnection in a stacked body of the first circuit substrate and the second circuit substrate so as to form a first opening in the top surface of the first interconnection and to form a second opening in the top surface of the second interconnection. The forming of the first circuit substrate includes forming an etching stopper layer on the surface of the first interconnection out of a material having an etching rate lower than that of the first interconnection in the etching process.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 21, 2014
    Applicant: Sony Corporation
    Inventor: Ikue Mitsuhashi
  • Patent number: 8691686
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first circuit substrate having a first interconnection; forming a second circuit substrate having a second interconnection; bonding the first circuit substrate to the top surface of the second circuit substrate so as to be stacked facing each other; and performing an etching process of simultaneously removing parts formed on the first interconnection and the second interconnection in a stacked body of the first circuit substrate and the second circuit substrate so as to form a first opening in the top surface of the first interconnection and to form a second opening in the top surface of the second interconnection. The forming of the first circuit substrate includes forming an etching stopper layer on the surface of the first interconnection out of a material having an etching rate lower than that of the first interconnection in the etching process.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventor: Ikue Mitsuhashi
  • Publication number: 20130020468
    Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 24, 2013
    Applicant: SONY CORPORATION
    Inventors: Ikue Mitsuhashi, Kentaro Akiyama, Koji Kikuchi
  • Publication number: 20120256319
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first circuit substrate having a first interconnection; forming a second circuit substrate having a second interconnection; bonding the first circuit substrate to the top surface of the second circuit substrate so as to be stacked facing each other; and performing an etching process of simultaneously removing parts formed on the first interconnection and the second interconnection in a stacked body of the first circuit substrate and the second circuit substrate so as to form a first opening in the top surface of the first interconnection and to form a second opening in the top surface of the second interconnection. The forming of the first circuit substrate includes forming an etching stopper layer on the surface of the first interconnection out of a material having an etching rate lower than that of the first interconnection in the etching process.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 11, 2012
    Applicant: SONY CORPORATION
    Inventor: Ikue Mitsuhashi