Abstract: The invention is directed to a chip size package (“CSP”) configuration and method for arranging a CSP configuration which is simple to manufacture, and less costly. The invention includes a structure for a printed circuit board (“PCB”), having at least a single pad for a chip size package (“CSP”) which is square shape. The CSP pad then is rotated 45 degrees in a clockwise or counter clockwise direction from a perpendicular so as to form a diamond shape. Also included is at least a via having a circle shape and wherein the distance between an inner side of the rotated CSP pad, where the inner side is the side closest to the via, and the outer edge of the via is at least 0.1 mm.

Abstract: An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has its gate coupled to the input node and its conducting path coupled in series with the output node and the first reference node. The first transistor operates to uncouple the output node from the first reference node in response to an input voltage applied to the input node. The noise immunity circuitry keeps the output node uncoupled from the first reference node during undershoot noise in a first reference voltage that causes the first transistor to change from an off state to an on state. The noise immunity circuitry includes second and third transistors. The second transistor has its gate coupled to the input node and its conducting path coupled in series with the conducting path of the first transistor. The third transistor is configured to keep the second transistor in an off state during the undershoot noise.

Abstract: An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has its gate coupled to the input node and its conducting path coupled in series with the output node and the first reference node. The first transistor operates to uncouple the output node from the first reference node in response to an input voltage applied to the input node. The noise immunity circuitry keeps the output node uncoupled from the first reference node during undershoot noise in a first reference voltage that causes the first transistor to change from an off state to an on state. The noise immunity circuitry includes second and third transistors. The second transistor has its gate coupled to the input node and its conducting path coupled in series with the conducting path of the first transistor. The third transistor is configured to keep the second transistor in an off state during the undershoot noise.

Abstract: The present invention is a method and apparatus for providing a four input logic function.

Abstract: The present invention is a method and apparatus for providing slew rate control. The apparatus comprises a first circuit and a second circuit having an output terminal that is coupled to a first end of the first circuit. The second circuit receives a first input signal and a second input signal. The apparatus further comprises a third circuit having an output terminal that is coupled to the first end of the first circuit. The third circuit also receives the first input signal and the second input signal. The first circuit generates an output signal having a predetermined slew rate, where the output signal has a first state when the first and second input signals are in a first state.

Abstract: A CMOS differential transmitter and matched receiver apparatus and method for transmitting data. The system uses a CMOS bias network to create low voltage swings and optimize the voltage offsets to compensate for variations caused by the manufacturing process, and thereby increase data transmission rates to approximately 1 gigabit per second.

Abstract: A circuit, system, and method for increasing the speed of a bus by reducing the capacitive loading effect of transistors coupled to the bus are provided. The transistors, which are sub-micrometer channel length CMOS transistors, make up a tranceiver comprised of a transmitter and a reciever. The transistors that make up the transciever are coupled to the bus through a pair of Schottky diodes in series. The diode pair is coupled to isolate the bus from the junction capacitance of the transistors. The bus is a multi-segment transmission line with a characteristic impedance. The opposite ends of the transmission line are terminated with the characteristic impedance of the transmission line. The voltage swing of the bus is limited to approximately 1 volt. The pair of Schottky diodes isolate the signal bus line from the capacitive loading effects of the transistor drivers used to drive the voltages on the transmitting end of the bus, especially when the bus is being pulled to a logic high level.

Abstract: A CMOS differential transmitter and matched receiver apparatus and method for transmitting data. The system uses a CMOS bias network to create low voltage swings and optimize the voltage offsets to compensate for variations caused by the manufacturing process, and thereby increase data transmission rates to approximately 1 gigabit per second.