Abstract: While modules to be tested in one constant temperature oven are tested by providing a plurality of constant temperature ovens, accommodating a plurality of modules to be tested in each constant temperature oven and connecting the modules to be tested accommodated in a plurality of constant temperature ovens to the measuring instruments via the switches, preparation for testing such as temperature change of the other constant temperature oven is conducted and the modules to be tested in one constant temperature oven are tested using measuring instruments. Thereafter, the switches are changed over and the modules to be tested accommodated in the other constant temperature oven are tested. Thereby, expensive measuring instruments can be used effectively.

Abstract: An ultra-thin resin molded semiconductor device of high reliability with low cost and with easy repair at time of mounting. A plurality of these semiconductor devices are stacked to provide a semiconductor module which has a higher function than semiconductor devices in the same volume, and a card type module utilizing assembled by the stacked semiconductor module is provided. In manufacturing the semiconductor module, an extremely thin lead frame and an LSI chip are directly connected together, and the mirror surface of the LSI chip is exposed by using a low viscosity epoxy resin to have a thin molding. The mirror surface is grinded to have a further thin thickness of the whole structure of the semiconductor device. A part of the lead frame is formed as a reinforcing member, a heat radiation path, a light shielding part for shielding the LSI from harmful light beams, or a positioning base for mounting a substrate.

Abstract: An external memory device subsystem and a data recording device, which issue a command specifying previously a plurality of tracks in a rotary type memory device prior to a read or write instruction issued from the data processing unit of higher rank to the rotary type memory device through a control unit; select continuously the plurality of tracks previously specified, at executing a read or write command after the execution of the command; and in this way can read/write continuously without wait time for rotation a plurality of tracks distant from each other within the same cylinder.

Abstract: An external memory device subsystem and a data recording device, which issue a command specifying a plurality of tracks (surfaces) in a rotary type memory device prior to a read or write instruction being issued from the data processing unit of higher rank to the rotary type memory device through a control unit; selects sequentially the plurality of individual tracks (surfaces) previously specified when executing a read or write command after the receipt of the command; and in this way can read/write continuously without wait time interruptions when data is discontinuous.

Abstract: A pattern generator permitting to output patterns at high speed and having an operating function, which is suitable for generating test patterns for memory ICs. Although it was known heretofore to increase the operating speed by operating a plurality of pattern generators, for which patterns were generated from memories, in which patterns were previously stored, in parallel, it was not possible to operate pattern generators having an operating function in parallel. A method, by which the order of execution of operation processing instructions is assigned to each of the pattern generators and operation processing instructions are accumulated and allows patterns to be generated at high speed by means of a pattern generator having an operating function. Specifically, the operating processing instructions are grouped and rearranged such that all the pattern generators execute instructions in parallel.

Abstract: A memory test apparatus for testing a high-performance memory having two or more memory functions, including a pattern generator for generating an algorithmic pattern to be inputted to a first memory block of a memory under test having at least two memory blocks, an auxiliary pattern generator for storing an output from the algorithmic pattern generator and for outputting an expected value to a second memory block of the memory under test at a preset timing based on the stored output, a comparator for comparing outputs from the first and second memory blocks with expected values for the memory blocks, and a memory for storing an output from the comparator.

Abstract: In a semiconductor testing device of LSI or the like, a high-speed small-capacity memory (50) is provided in addition to low-speed large-capacity memories (11.about.14) for interleave operation, and test patterns after a branch operation are previously stored in the memory (50). When test patterns are to be read in sequence the reading is performed from the low-speed large-capacity memories (11.about.14), and when branch is produced in the reading sequence the changing is performed to the high-speed small-capacity memory (50) and the test patterns are read from the high-speed small-capacity memory (50) until the reading from the low-speed large-capacity memories (11.about.14) again becomes possible. Thereby, the test patterns of a large number can be outputted without generating a dummy cycle.

Abstract: Only that data which relates to detected failures of data stored in a memory under test is stored in a compressed data matrix of a small capacity which is determined by a predetermined number of redundant lines to be selected for remedy of the failures, and the selection of the redundant lines is effected during the execution of a test on the memory. Analysis leading to redundant line selection is effected on the data stored in this compressed matrix.

Abstract: A bit pattern generator includes two memories which are provided for storing a bit pattern for a scanning line produced from design data. When a bit pattern is created and stored in one of the memories, the previously created and stored bit pattern is read out from the other memory. For the creation of each bit pattern, a scanning line is divided into a plurality of bytes. Model patterns of bit patterns existing in the respective bytes are stored in a ROM. From the combination of start point and end point addresses specifying the byte positions and the ROM addresses, a ROM address for each byte is logically determined so that any model patterns in the ROM are sequentially stored in the first mentioned memories.

Abstract: A pattern signal for sequentially displaying crisscross patterns of three primary colors of red, green and blue is supplied to a color picture tube. Two television cameras pick up the pattern images displayed on the color picture tube through a 1:1 half mirror. The line scanning directions of the first and second television cameras are horizontal and vertical respectively with respect to the CRT display screen. The aspect ratio of the first television camera is selected to be equal to that of the CRT display screen, and the aspect ratio of the second television camera is selected to be equal to the reciprocal of that of the CRT display screen. The image output signals of these two television cameras are selectively supplied to an image processing circuit by a change-over unit. In this image processing circuit, a counter counts the time-related positions of peak values appearing within a specified line scanning period in the image signals supplied through the change-over unit.