Patents by Inventor Ikuo Kudo
Ikuo Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8572425Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: July 19, 2012Date of Patent: October 29, 2013Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
-
Patent number: 8525294Abstract: A package-on-package includes a semiconductor package, and a coil provided at the semiconductor package. The semiconductor package includes a bottom face, and a solder ball protruded from the bottom face. An axis of the coil is inclined with respect to the normal line of the bottom face.Type: GrantFiled: July 2, 2009Date of Patent: September 3, 2013Assignee: Renesas Electronics CorporationInventors: Akira Tada, Hiroki Tanabe, Yoshinori Okada, Ikuo Kudo
-
Patent number: 8327180Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: June 3, 2011Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
-
Publication number: 20120284554Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Inventors: KAZUO SAKAMOTO, Naozumi MORINO, Ikuo KUDO
-
Publication number: 20110272781Abstract: A package-on-package includes a semiconductor package, and a coil provided at the semiconductor package. The semiconductor package includes a bottom face, and a solder ball protruded from the bottom face. An axis of the coil is inclined with respect to the normal line of the bottom face.Type: ApplicationFiled: July 2, 2009Publication date: November 10, 2011Inventors: Akira Tada, Hiroki Tanabe, Yoshinori Okada, Ikuo Kudo
-
Publication number: 20110231694Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Inventors: KAZUO SAKAMOTO, Naozumi Morino, Ikuo Kudo
-
Patent number: 7966512Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: January 4, 2009Date of Patent: June 21, 2011Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
-
Publication number: 20090113231Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: ApplicationFiled: January 4, 2009Publication date: April 30, 2009Inventors: Kazuo SAKAMOTO, Naozumi Morino, Ikuo Kudo
-
Patent number: 7490258Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: April 20, 2004Date of Patent: February 10, 2009Assignee: Renesas Technology Corp.Inventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
-
Patent number: 7286386Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.Type: GrantFiled: April 11, 2006Date of Patent: October 23, 2007Assignee: Renesas Technology Corp.Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
-
Publication number: 20060180943Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.Type: ApplicationFiled: April 11, 2006Publication date: August 17, 2006Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
-
Patent number: 7061785Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.Type: GrantFiled: June 27, 2003Date of Patent: June 13, 2006Assignee: Renesas Technology Corp.Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
-
Publication number: 20040243877Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: ApplicationFiled: April 20, 2004Publication date: December 2, 2004Applicant: Renesas Technology Corp.Inventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
-
Publication number: 20040027869Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.Type: ApplicationFiled: June 27, 2003Publication date: February 12, 2004Applicant: Hitachi, Ltd.Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
-
Patent number: 5819221Abstract: Improved speech recognition is achieved according to the present invention by use of between word and/or between phrase coarticulation. The increase in the number of phonetic models required to model this additional vocabulary is reduced by clustering 19, 20 the inter-word/phrase models and grammar into only a few classes. By using one class for consonant inter-word context and two classes for vowel contexts, the accuracy for Japanese was almost as good as for unclustered models while the number of models was reduced more than half.Type: GrantFiled: August 31, 1994Date of Patent: October 6, 1998Assignee: Texas Instruments IncorporatedInventors: Kazuhiro Kondo, Ikuo Kudo, Yu-Hung Kao, Barbara J. Wheatley