Patents by Inventor Ikuo Kudo

Ikuo Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8572425
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: October 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
  • Patent number: 8525294
    Abstract: A package-on-package includes a semiconductor package, and a coil provided at the semiconductor package. The semiconductor package includes a bottom face, and a solder ball protruded from the bottom face. An axis of the coil is inclined with respect to the normal line of the bottom face.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Tada, Hiroki Tanabe, Yoshinori Okada, Ikuo Kudo
  • Patent number: 8327180
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
  • Publication number: 20120284554
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Application
    Filed: July 19, 2012
    Publication date: November 8, 2012
    Inventors: KAZUO SAKAMOTO, Naozumi MORINO, Ikuo KUDO
  • Publication number: 20110272781
    Abstract: A package-on-package includes a semiconductor package, and a coil provided at the semiconductor package. The semiconductor package includes a bottom face, and a solder ball protruded from the bottom face. An axis of the coil is inclined with respect to the normal line of the bottom face.
    Type: Application
    Filed: July 2, 2009
    Publication date: November 10, 2011
    Inventors: Akira Tada, Hiroki Tanabe, Yoshinori Okada, Ikuo Kudo
  • Publication number: 20110231694
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Application
    Filed: June 3, 2011
    Publication date: September 22, 2011
    Inventors: KAZUO SAKAMOTO, Naozumi Morino, Ikuo Kudo
  • Patent number: 7966512
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Grant
    Filed: January 4, 2009
    Date of Patent: June 21, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
  • Publication number: 20090113231
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Application
    Filed: January 4, 2009
    Publication date: April 30, 2009
    Inventors: Kazuo SAKAMOTO, Naozumi Morino, Ikuo Kudo
  • Patent number: 7490258
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: February 10, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
  • Patent number: 7286386
    Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: October 23, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
  • Publication number: 20060180943
    Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.
    Type: Application
    Filed: April 11, 2006
    Publication date: August 17, 2006
    Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
  • Patent number: 7061785
    Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: June 13, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
  • Publication number: 20040243877
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Application
    Filed: April 20, 2004
    Publication date: December 2, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
  • Publication number: 20040027869
    Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function.
    Type: Application
    Filed: June 27, 2003
    Publication date: February 12, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
  • Patent number: 5819221
    Abstract: Improved speech recognition is achieved according to the present invention by use of between word and/or between phrase coarticulation. The increase in the number of phonetic models required to model this additional vocabulary is reduced by clustering 19, 20 the inter-word/phrase models and grammar into only a few classes. By using one class for consonant inter-word context and two classes for vowel contexts, the accuracy for Japanese was almost as good as for unclustered models while the number of models was reduced more than half.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: October 6, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Kazuhiro Kondo, Ikuo Kudo, Yu-Hung Kao, Barbara J. Wheatley