Patents by Inventor Ikuo Kurachi

Ikuo Kurachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145519
    Abstract: To provide a photo detection device and a manufacturing method thereof, the photo detection device comprising a SPAD in which a substrate-manufacturing cost is kept sufficiently low compared to InGaAs, afterpulsing is less and DCR is also reduced. A photo detection device detecting an incident light from an object, comprising: (i) a P-type silicon (Si) substrate; (ii) a P-type germanium (Ge) layer formed by epitaxial growth on a first surface serving as a front surface of the P-type silicon (Si) substrate; and (iii) a P-type thin film silicon (Si) layer formed on the P-type germanium (Ge) layer, (iv) wherein the P-type thin film silicon (Si) layer is divided into a first region and a second region by a Shallow Trench Isolation (STI), multiple single photon avalanche diodes (SPADs) arranged in an array are formed in the first region, and a CMOS transistor circuit driving the SPADs is formed in the second region.
    Type: Application
    Filed: March 16, 2022
    Publication date: May 2, 2024
    Applicant: Optohub Co., Ltd
    Inventors: Ikuo KURACHI, Hiroshi TAKANO, Yasumasa KASHIMA
  • Publication number: 20220199661
    Abstract: The semiconductor image sensor of the present invention comprises a light receiving element formed in a silicon substrate under an insulation film of an SOI substrate comprising the silicon substrate, the insulation film formed on the silicon substrate, and a semiconductor layer formed on the insulation film, and composed of a pn junction diode formed in a vertical direction to a main surface of the silicon substrate and having sensitivity to near-infrared light, and a high voltage generating circuit configured to generate an applied voltage for applying a reverse bias voltage to the pn junction diode, and an impurity concentration of the silicon substrate is in a range of 1×1012/cm3 to 1×1014/cm3, a film thickness is in a range of 300 ?m to 700 ?m, and the applied voltage is in a range of 10 V to 60 V.
    Type: Application
    Filed: April 10, 2020
    Publication date: June 23, 2022
    Applicant: Optohub Co., Ltd
    Inventors: Ikuo KURACHI, Hiroshi TAKANO, Yasumasa KASHIMA
  • Publication number: 20210119039
    Abstract: A power semiconductor device is provided, in which a high breakdown voltage and a large current are possible, and a low on-voltage, a low switching loss, and low noise are realized. A second conductivity type block layer is provided on at least one of a first conductivity type SiC substrate, on which a SiC drift layer is formed, and a second conductivity type Si substrate, a trench gate is then provided, by bonding the SiC substrate and the Si substrate, to reach at least a part of the SiC drift layer from the Si substrate side, and a Si-MOSFET having high channel mobility and the SiC drift layer having high bulk mobility and a high breakdown voltage are combined.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 22, 2021
    Applicant: EASTWIND, LLC.
    Inventors: Takashi Miida, Ikuo Kurachi
  • Patent number: 10908120
    Abstract: A semiconductor biosensor includes a central reaction unit of an inspection equipment. The central reaction unit includes a plurality of first conducting wires, a plurality of second conducting wires, a common electrode source, a plurality of sense-amplifiers, a plurality of non-volatile memory type transistors, and a first oxide film. Each sense-amplifier is connected to a respective second conducting wire. The non-volatile memory type transistors are respectively formed on the second conducting wires. Each non-volatile memory type transistor includes a control gate, a third oxide film, a floating gate, and a second oxide. The first oxide film wraps or covers the first conducting wires. Receptors are fixed on a surface of the first oxide film. A portion of the targets couples with a portion of the receptors to form composite bodies. The sense-amplifiers are configured to detect a change in a current signal based on the charges of the composite bodies.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 2, 2021
    Assignee: Laurus Corporation
    Inventors: Hiroshi Watanabe, Zhe-An Lee, Ikuo Kurachi
  • Patent number: 10418985
    Abstract: The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the radiation-damage-compensation-circuit to recover the characteristics of the SOI-MOSFET after X-ray irradiation.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: September 17, 2019
    Assignees: INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION, HIGH ENERGY ACCELERATION RESEARCH ORGANIZATION
    Inventors: Ikuo Kurachi, Yasuo Arai, Miho Yamada
  • Publication number: 20190154631
    Abstract: A semiconductor biosensor includes a central reaction unit of an inspection equipment. The central reaction unit includes a plurality of first conducting wires, a plurality of second conducting wires, a common electrode source, a plurality of sense-amplifiers, a plurality of non-volatile memory type transistors, and a first oxide film. Each sense-amplifier is connected to a respective second conducting wire. The non-volatile memory type transistors are respectively formed on the second conducting wires. Each non-volatile memory type transistor includes a control gate, a third oxide film, a floating gate, and a second oxide. The first oxide film wraps or covers the first conducting wires. Receptors are fixed on a surface of the first oxide film. A portion of the targets couples with a portion of the receptors to form composite bodies. The sense-amplifiers are configured to detect a change in a current signal based on the charges of the composite bodies.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Inventors: Hiroshi Watanabe, ZHE-AN LEE, IKUO KURACHI
  • Publication number: 20190131965
    Abstract: The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the radiation-damage-compensation-circuit to recover the characteristics of the SOI-MOSFET after X-ray irradiation.
    Type: Application
    Filed: October 6, 2016
    Publication date: May 2, 2019
    Applicant: Inter-University Research Institute Corporation High Energy Accelerator Research Organization
    Inventors: Ikuo Kurachi, Yasuo Arai, Miho Yamada
  • Publication number: 20150255614
    Abstract: A split gate flash memory is provided. A device isolation structure is disposed in a substrate to define an active area. A first doping region and a second doping region are respectively disposed in an active area of the substrate. A select gate is disposed in a trench in the substrate, and a side of the select gate is adjacent to the first doping region. A gate dielectric layer is disposed between the select gate and the substrate. A floating gate is disposed on the substrate, a side of the floating gate overlaps to the second doping region, and a portion of the floating gate is disposed on the select gate. An inter-gate dielectric layer is disposed between the floating gate and the select gate and between the floating gate and the substrate.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Applicant: Powerchip Technology Corporation
    Inventors: Yukihiro Nagai, Ikuo Kurachi
  • Patent number: 8557719
    Abstract: A method for fabricating a semiconductor device, according to the present invention includes the steps of: preparing an SOI substrate, which comprises a semiconductor supporting layer, an oxide layer formed on the semiconductor supporting layer and an SOI layer formed on the oxide layer; forming a semiconductor device on the SOI layer; forming a passivation layer over the SOI substrate, the passivation layer allowing a UV light to pass through it; and applying a UV light to the SOI substrate after the step of forming the semiconductor device is completed.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 15, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Wataru Shimizu, Ikuo Kurachi
  • Patent number: 7776691
    Abstract: The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: August 17, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Takaharu Nakamura, Tetsuhiro Maruyama, Masao Tsujimoto, Ikuo Kurachi
  • Patent number: 7732783
    Abstract: An ultraviolet light monitoring system includes first and second electrodes, an evaluation subject film and a power source. The first and second electrodes are opposingly disposed and attract holes which are generated in accordance with irradiation of ultraviolet light. The evaluation subject film is formed in a vicinity of the first and second electrodes, and is a subject of evaluation of damage caused by the irradiation of ultraviolet light. The power source, at times of monitoring of the ultraviolet light, applies a predetermined bias to a series path formed by the first electrode, a gap between the first and second electrodes, and the second electrode.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: June 8, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Jun Hashimoto, Shinji Kawada, Ikuo Kurachi, Seiji Samukawa
  • Patent number: 7714370
    Abstract: A semiconductor storage device includes: a MOSFET formed on an SOI layer of the transistor forming region; and a MOS capacitor formed on the SOI layer of the capacitor forming region. The MOSFET includes: a gate insulating film formed; a floating gate electrode; a source layer and a drain layer formed; a channel region; a high-concentration diffusion layer, and impurities of a same type as impurities which are diffused in the channel region are diffused at a high concentration in the high-concentration diffusion layer; and a silicide layer covering the high-concentration diffusion layer and the source layer. The MOS capacitor includes a capacitor electrode at the SOI layer. The capacitor electrode of the MOS capacitor is disposed so as to oppose an end portion of the floating gate electrode of the MOSFET, with the gate insulating film therebetween.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: May 11, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Ikuo Kurachi
  • Publication number: 20090209111
    Abstract: A method for fabricating a semiconductor device, according to the present invention includes the steps of: preparing an SOI substrate, which comprises a semiconductor supporting layer, an oxide layer formed on the semiconductor supporting layer and an SOI layer formed on the oxide layer; forming a semiconductor device on the SOI layer; forming a passivation layer over the SOI substrate, the passivation layer allowing a UV light to pass through it; and applying a UV light to the SOI substrate after the step of forming the semiconductor device is completed.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 20, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Wataru Shimizu, Ikuo Kurachi
  • Publication number: 20090058432
    Abstract: An ultraviolet light monitoring system includes first and second electrodes, an evaluation subject film and a power source. The first and second electrodes are opposingly disposed and attract holes which are generated in accordance with irradiation of ultraviolet light. The evaluation subject film is formed in a vicinity of the first and second electrodes, and is a subject of evaluation of damage caused by the irradiation of ultraviolet light. The power source, at times of monitoring of the ultraviolet light, applies a predetermined bias to a series path formed by the first electrode, a gap between the first and second electrodes, and the second electrode.
    Type: Application
    Filed: July 17, 2008
    Publication date: March 5, 2009
    Applicants: OKI ELECTRIC INDUSTRY CO., LTD., TOHOKU UNIVERSITY
    Inventors: Jun Hashimoto, Shinji Kawada, Ikuo Kurachi, Seiji Samukawa
  • Publication number: 20090053868
    Abstract: The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory.
    Type: Application
    Filed: October 17, 2008
    Publication date: February 26, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Takaharu Nakamura, Tetsuhiro Maruyama, Masao Tsujimoto, Ikuo Kurachi
  • Patent number: 7462896
    Abstract: The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 9, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takaharu Nakamura, Tetsuhiro Maruyama, Masao Tsujimoto, Ikuo Kurachi
  • Publication number: 20070272956
    Abstract: A control electrode is provided via an insulating film on one main surface of a semiconductor substrate having a first conductivity type. A pair of dopant diffusion regions are formed, with the control electrode therebetween, in a surface layer region of the semiconductor substrate. Resistance variation sections are formed in the surface layer region of the semiconductor substrate between the control electrode and the dopant diffusion regions. The resistance variation sections are of the second conductivity type and have a dopant concentration lower than that of the dopant diffusion regions. First and second main electrodes are provided on the dopant diffusion regions of the semiconductor substrate. A first charge storage section is provided between the first main electrode and control electrode on the semiconductor substrate. A second charge storage section is provided between the second main electrode and control electrode on the semiconductor substrate.
    Type: Application
    Filed: April 19, 2007
    Publication date: November 29, 2007
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Ikuo Kurachi, Toshiyuki Orita
  • Publication number: 20070228467
    Abstract: A semiconductor storage device includes: a MOSFET formed on an SOI layer of the transistor forming region; and a MOS capacitor formed on the SOI layer of the capacitor forming region. The MOSFET includes: a gate insulating film formed; a floating gate electrode; a source layer and a drain layer formed; a channel region; a high-concentration diffusion layer, and impurities of a same type as impurities which are diffused in the channel region are diffused at a high concentration in the high-concentration diffusion layer; and a silicide layer covering the high-concentration diffusion layer and the source layer. The MOS capacitor includes a capacitor electrode at the SOI layer. The capacitor electrode of the MOS capacitor is disposed so as to oppose an end portion of the floating gate electrode of the MOSFET, with the gate insulating film therebetween.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 4, 2007
    Inventor: Ikuo Kurachi
  • Patent number: 7199030
    Abstract: An impurity is ion-implanted with a silicon nitride film formed on a silicon substrate as a mask film to form a source/drain layer of a MOS transistor. Heat treatment for activating the impurity is done as it is without removing the silicon nitride film to thereby produce heat treatment-based stress between the silicon nitride film and the silicon substrate.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: April 3, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Satoshi Ikeda, Yutaka Kamata, Ikuo Kurachi, Norio Hirashita
  • Publication number: 20070023824
    Abstract: The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory.
    Type: Application
    Filed: June 29, 2006
    Publication date: February 1, 2007
    Inventors: Takaharu Nakamura, Tetsuhiro Maruyama, Masao Tsujimoto, Ikuo Kurachi