Patents by Inventor Ikuo Nakashima
Ikuo Nakashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11935848Abstract: Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.Type: GrantFiled: November 10, 2022Date of Patent: March 19, 2024Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Ikuo Nakashima, Shingo Inoue
-
Publication number: 20230198169Abstract: A semiconductor device includes a base, a matching circuit including a substrate, a ground layer, and a signal line, wherein a width of the signal line on a first end side of the substrate is smaller than a width of the substrate and larger than that of the signal line on a second end side, and a distance between the ground layer and the signal line on the first end side is larger than a distance therebetween on the second end side, a semiconductor element electrically connected to the signal line on the first end side of the matching circuit by first bonding wires, a frame body, a feedthrough having a lead, and second bonding wires electrically connected to the lead and the signal line on the second end side, wherein the first bonding wires are arranged in parallel, and the second bonding wires are arranged in parallel.Type: ApplicationFiled: May 12, 2021Publication date: June 22, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Ikuo NAKASHIMA
-
Publication number: 20230076573Abstract: Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.Type: ApplicationFiled: November 10, 2022Publication date: March 9, 2023Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Ikuo NAKASHIMA, Shingo INOUE
-
Patent number: 11557553Abstract: Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.Type: GrantFiled: July 29, 2020Date of Patent: January 17, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Ikuo Nakashima, Shingo Inoue
-
Publication number: 20210035931Abstract: Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.Type: ApplicationFiled: July 29, 2020Publication date: February 4, 2021Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Ikuo NAKASHIMA, Shingo INOUE
-
Patent number: 9743557Abstract: An amplifier module having a surface-mounting carrier with a base and lid is disclosed. The base in a top surface thereof provides a die pad on which a transistor is mounted, and a back surface thereof provides a back pad electrically and thermally connected to the die pad. The back pad has an area wider than the area of the die pad. The heat conduction from the transistor to the host board on which the amplifier module is mounted is effectively enhanced.Type: GrantFiled: August 27, 2015Date of Patent: August 22, 2017Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Ikuo Nakashima, Naoto Murata
-
Publication number: 20160065145Abstract: An amplifier module having a surface-mounting carrier with a base and lid is disclosed. The base in a top surface thereof provides a die pad on which a transistor is mounted, and a back surface thereof provides a back pad electrically and thermally connected to the die pad. The back pad has an area wider than the area of the die pad. The heat conduction from the transistor to the host board on which the amplifier module is mounted is effectively enhanced.Type: ApplicationFiled: August 27, 2015Publication date: March 3, 2016Inventors: Ikuo NAKASHIMA, Naoto MURATA
-
Patent number: 5622602Abstract: An apparatus for controlling the degree of fiber variations in paper sheet has a formation meter for receiving an image of transmitted light on one side of an area of paper from a light source located on the other side of the area of paper, an image processing computing element for introducing the image from said formation meter for image processing and a fuzzy control unit for calculating and outputting optimum J/W ratio, optimum foil angle, and optimum deflector pushing degree and angle on the basis of results of image processing from said image processing computing element.Type: GrantFiled: December 13, 1994Date of Patent: April 22, 1997Assignee: Ishikawajima-Harima Jukogyo Kabushiki KaishaInventors: Masahiro Yakabe, Satoshi Suzuki, Sadao Degawa, Shigeki Murayama, Koichi Ishibashi, Ikuo Nakashima, Koji Sakai
-
Patent number: 5393378Abstract: A formation control method and apparatus in which an image is emitted from a light source and transmitted through a predetermined area of paper an captured by a camera to be displayed as transmitted light image on a display of an image processing computing element, the transmitted light image displayed on the display being image-analyzed to obtain formation factor for quantification of the formation, J/W ratio and the like being optimized by fuzzy control using membership functions based on said formation factor so as to improve the formation.Type: GrantFiled: March 2, 1993Date of Patent: February 28, 1995Assignee: Ishikawajima-Harima Jukogyo Kabushiki KaishiInventors: Masahiro Yakabe, Satoshi Suzuki, Sadao Degawa, Shigeki Murayama, Koichi Ishibashi, Ikuo Nakashima, Koji Sakai
-
Patent number: D709495Type: GrantFiled: May 28, 2013Date of Patent: July 22, 2014Assignees: Japan Radio Co., Ltd., Eizo CorporationInventors: Keiko Akutsu, Shigeru Namaizawa, Makoto Nakanishi, Masaki Nakamura, Shinichi Honda, Ikuo Nakashima
-
Patent number: D709496Type: GrantFiled: May 28, 2013Date of Patent: July 22, 2014Assignee: Eizo CorporationInventors: Masaki Nakamura, Shinichi Honda, Ikuo Nakashima
-
Patent number: D709497Type: GrantFiled: May 28, 2013Date of Patent: July 22, 2014Assignees: Japan Radio Co., Ltd., Eizo CorporationInventors: Keiko Akutsu, Shigeru Namaizawa, Makoto Nakanishi, Masaki Nakamura, Shinichi Honda, Ikuo Nakashima
-
Patent number: D709879Type: GrantFiled: May 28, 2013Date of Patent: July 29, 2014Assignee: Eizo CorporationInventors: Masaki Nakamura, Shinichi Honda, Ikuo Nakashima