Abstract: Disclosed herein are a structure of and a method of manufacturing a semiconductor device which can relatively readily form a high-concentration impurity layer or a three-layer LDD structure for reducing contact resistance in a source/drain region in high accuracy.In the method of manufacturing a semiconductor device, deposition of an oxide insulating film and anisotropic etching thereof are carried out a plurality of times, and the anisotropic etching is carried out in a state covering one side wall of a gate electrode part with a mask at least once in the plurality of times thereby forming side wall spacers having different widths on both side walls of the gate electrode part respectively, while the side wall spacer provided on one of the side walls is employed as a mask to form a high-concentration n-type impurity layer to be inside the source/drain region on a semiconductor substrate surface corresponding to this side.

Abstract: A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors.

Abstract: A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors.

Abstract: A lightly doped drain MOSFET has lightly doped portions on both the source and drain sides, with the drain side lightly doped portion being wider. The assymetrical structure may be provided by using different width sidewall spacers.

Abstract: A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit.

Abstract: A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2.

Abstract: A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors.

Abstract: A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Abstract: A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

Abstract: A DRAM having stacked capacitor cell comprises one transfer gate transistor and one capacitor. A thick insulating film having flat surface is formed on the surface of the transfer gate transistor and the like. A conductive film is formed on a surface of one impurity region of the transfer gate transistor. An opening portion deep enough to reach the conductive film is formed in the insulating film. The capacitor is formed in the opening portion and on the upper surface of the insulating film. A lower electrode of the capacitor is connected to the conductive film. An insulating film having a flat surface is formed by a reflow process employing thermal processing, plasma ECR CVD method and the like.

Abstract: A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Abstract: A method of forming a resist pattern on a main surface of a semiconductor substrate comprising the steps of exposing a resist to light and developing it to become a predetermined pattern, curing the surface of the resist pattern formed by the exposing and developing treatments by irradiating the surface with far ultraviolet rays having a short wavelength, and baking the resist pattern subjected to a light irradiation treatment. The light irradiation treatment is performed by irradiating the surface of the resist pattern, which is not shaded from light with the far ultraviolet rays, in a state in which a resist pattern region formed on a peripheral portion of the semiconductor substrate is shaded from light. As a result, a crack can be prevented from forming on the resist of the peripheral portion of the semiconductor substrate. A light irradiation apparatus used in the light irradiation treatment comprises shading means for selectively intercepting the irradiation light.

Abstract: A conductive resist film is used as a mask in ion implantation. A portion of the conductive resist film is electrically connected to a semiconductor substrate. The charge of ions which enter the conductive resist film in ion implantation flows into the semiconductor substrate and dissipates therein.

Abstract: A method of forming a resist pattern on a main surface of a semiconductor substrate comprising the steps of exposing a resist to light and developing it to become a predetermined pattern, curing the surface of the resist pattern formed by the exposing and developing treatments by irradiating the surface with far ultraviolet rays having a short wavelength, and baking the resist pattern subjected to a light irradiation treatment. The light irradiation treatment is performed by irradiating the surface of the resist pattern, which is not shaded from light with the far ultraviolet rays, in a state in which a resist pattern region formed on a peripheral portion of the semiconductor substrate is shaded from light. As a result, a crack can be prevented from forming on the resist of the peripheral portion of the semiconductor substrate. A light irradiation apparatus used in the light irradiation treatment comprises shading means for selectively intercepting the irradiation light.

Abstract: Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.

Abstract: A cell plate (6) is formed on a main surface of a semiconductor substrate (7) with an insulating film (8) interposed therebetween and an interconnection (1) having T-shape cross section is formed on the cell plate (6) with an interlayer insulating film (11) interposed therebetween. An upper insulating film (12) is formed to cover the interconnection (1).

Abstract: A silicon oxide film and a BPSG film are formed on a silicon substrate to serve as insulating films, and a contact hole is selectively formed in the insulating films. An impurity diffusion layer is formed on the surface layer of the semiconductor substrate at the bottom portion of the contact hole. A second metal film serving as a metal electrode is formed to cover the BPSG film and the impurity diffusion layer, and a first metal film serving as a barrier layer is formed between the second metal film and the BPSG film and impurity diffusion layer. The first metal film prevents boron contained in the BPSG film from being diffused in the second metal film, thereby to prevent precipitation of silicon in the contact hole.

Abstract: In a method according to the present invention for forming isolation oxide films (14) on a silicon substrate (11) having trenches and islands bounded by the trenches, the isolation oxide films are simultaneously formed in the island regions and in the side wall regions of the trenches by oxidizing the substrate (11) with a single patterned oxidation mask (12).