Abstract: A pre-fetch prediction table is provided for storing history of readout access given from a host device. A controller in a disk control device registers entry information including a set of an area address a indicating the access destination of the previous access and concerned prediction address b, having an area address b indicating the access destination of the readout access given from the host device as prediction address b, into a corresponding entry of the pre-fetch prediction table. Thereafter, when a readout access designating the area address a in agreement with the area address a in the concerned entry information is given from the host device, the controller pre-fetches from a HDD to a disk cache according to the prediction address b in the concerned entry information.

Abstract: A plurality of disk array systems are realized in a single disk array apparatus, and double protection of disk arrays is achieved, whereby reliability is enhanced. Row-directional hard disk drives (HDD) connected to hard disk (HD) controllers constitute RAID4 groups. Column-directional HDDs constitute RAID3 groups. A disk region of each HDD is divided into a RAID3&4 region for storing large-volume data which is used repeatedly for a long time period, a RAID3 region for storing large-volume data which is used only for a predetermined time period, and a RAID4 region for storing small-volume data. The RAID3&4 region is protected by RAID3 and RAID4, the RAID3 region is protected by RAID3, and the RAID4 region is protected by RAID4.

Abstract: In executing indivisible operations to be executed without being interrupted, pseudo-store instructions PST which do not perform data writing are used to perform a check for the presence or absence in a memory of pages necessary for execution of the indivisible operations. In the event of absence of the necessary pages, the necessary pages are pre-stored in the memory. This prevents the generation of page fault interruptions during the execution of an indivisible operation, thereby enabling the indivisible operation to be implemented on a software basis. A disable interrupt instruction is executed prior to the execution of the indivisible operation as required, and data indicating an address of the disable interrupt instruction is preserved in order to return to the disable interrupt instruction.

Abstract: The shared disk array which incorporates a plurality of disk apparatus storing the contents including the digitized video data and a plurality of element servers are connected to the shared channel network suitable for the multi-initiator architecture, whereby each of the element servers can physically share the shared disk array via the shared channel network. Further, each of the element servers is provided with the network interface suitable for the high-speed transmission and the band-width reservation, so that the contents stored in the shared disk array are read out in response to the request form the client, thus being output of the communication network via the network interface.

Abstract: A technique for preventing downtime in a redundant computer system having several processors without disconnecting any of the processors from the system. When an abnormality of a processor is detected, a pulse signal which assumes a HIGH value at a predetermined period is supplied to a busy controller of the processor to set the processor in a waiting state. In response to the HIGH value of this signal, the busy controller outputs a busy signal to set the processor in a waiting state and shifts an execution timing of data processing of the processor from that of a normal state, thereby preventing recurrence of the abnormality.

Abstract: An error information saving apparatus of a computer includes at least one arithmetic unit, a plurality of storage units, and a control unit, connected to the storage units and the arithmetic unit, for controlling these units to perform a predetermined pipeline operation, wherein the storage units comprise an arithmetic register file consisting of a plurality of registers each of which can be designated as a destination operand in a statement of an operation instruction, a status flag string consisting of a plurality of flags provided in a one-to-one correspondence with the registers of the arithmetic register file, and a destination register number holding unit for sequentially saving and holding the numbers of destination registers of all operations performed while error interrupt processing generated after occurrence of an error is delayed by a predetermined time interval, each time one of the operations is completed.

Abstract: A virtual address register for storing a virtual address is arranged in a translation lookaside buffer control system. An artihmetic operation circuit is coupled to the virtual address register and performs adding, EX-ORing, and the like of the contents of two first fields which do not overlap each other. A TLB address register is coupled to the arithmetic operation circuit and the virtual address register, and stores the contents of a second field which does not overlap those of the first fields and output data from the arithmetic operation circuit. A translation lookaside buffer (TLB) is coupled to the TLB address register. The TLB is addressed by the content of the address register, stores address translation data in each entry, and translates a virtual address into a physical address, at high speed.

Abstract: In this invention, when a service processor must request processing to all of n processors, it supplies a processing request to one of the n processors using a 1:1 inter-processor communication instruction. The processor receiving the request from the service processor then supplies a processing request to the remaining (n-1) processors using a 1:n inter-processor communication instruction. A bus control unit for controlling a system bus has a flag indicating whether or not the 1:1 (or 1:n) inter-processor communication instruction is sent. The service processor and other processors refer to the flag. When the flag is ON, issuance of the 1:1 (or 1:n) inter-processor communication instruction is inhibited to prevent contention between a plurality of requests.