Patents by Inventor Ikuo Yasui

Ikuo Yasui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250051322
    Abstract: Crystals of compounds represented by formula (I) having potential as drug substances for pharmaceuticals, as well as salts of compounds represented by formula (I) and their crystals.
    Type: Application
    Filed: January 12, 2023
    Publication date: February 13, 2025
    Inventors: Ikuo Kushida, Yoko Ito, So Yasui, Takashi Fukuyama, Nobuaki Sato, Taro Asaba
  • Publication number: 20040190653
    Abstract: An initial value register stores gain control amount initial value at the start of a reception frame. At the start of reception frame, a latch unit outputs the value of the gain control amount initial value that has been taken in from initial value register and latched at the end of previous reception frame as a gain control value. A variable gain amplifier amplifies a signal received from mixer in accordance with this initial value. Thereafter, the gain of variable gain amplifier is controlled by a feedback loop structured with an RSSI circuit, a gain control circuit, and a D/A converter circuit, such that the signal level of a reception signal is stabilized at a prescribed level.
    Type: Application
    Filed: September 22, 2003
    Publication date: September 30, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Ikuo Yasui, Hisayasu Sato
  • Patent number: 5162667
    Abstract: A semiconductor integrated circuit of master and slave latches and the like that reduces power consumption by supplying a second clock which is a synchronous with a first clock to a slave latch only when the first clock that determines the latch period is supplied to a master latch, discontinuing the supply of the second clock after the master latch completes its latch action in the case that the supply of the first clock to the master latch is discontinued, and discontinuing the supply of clocks when latch action is not required, to reduce loads connected to them.
    Type: Grant
    Filed: November 7, 1990
    Date of Patent: November 10, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ikuo Yasui, Toru Kengaku, Eiichi Teraoka
  • Patent number: 5034887
    Abstract: A microprocessor utilizing Harvard Architecture is disclosed with a data space for data storage, an instruction space for instruction storage, and a common space implemented as a high-speed on-chip RAM that functions as a continuous extension of both the data space and the instruction space, for the simultaneous and flexible storage of data and instructions.
    Type: Grant
    Filed: July 27, 1990
    Date of Patent: July 23, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ikuo Yasui, Yukihiko Shimazu
  • Patent number: 4870609
    Abstract: The operation speed of a full adder is increased by avoiding the necessity of forming the inverse signal for adder operation and deleting the time required for passing through an inverter.
    Type: Grant
    Filed: October 26, 1987
    Date of Patent: September 26, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ikuo Yasui, Yukihiko Shimazu, Toru Kengaku