Abstract: Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals IN1 to IN3 are supplied to diffusion layer regions 221, 223 and 225 via transistors 301 to 303, and are accumulated as electric charge. A clock signal is applied to signal lines 121 and 122 alternately connected to gate electrodes 211 to 216, thus allowing the accumulated electric charge to be transferred to the right direction. Electric charge/voltage conversion amplifiers 411 to 413 are connected to the diffusion layer regions 221, 223 and 225, and the accumulated electric charge is converted into voltage and is output to output terminals VOUT1 to VOUT3 as analog signals. A scan-in terminal Sin is connected to a diffusion layer region 220, and a scan-out terminal Sout is connected to the diffusion layer region 225 via an electric charge/voltage conversion amplifier 401.

Abstract: Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals IN1 to IN3 are supplied to diffusion layer regions 221, 223 and 225 via transistors 301 to 303, and are accumulated as electric charge. A clock signal is applied to signal lines 121 and 122 alternately connected to gate electrodes 211 to 216, thus allowing the accumulated electric charge to be transferred to the right direction. Electric charge/voltage conversion amplifiers 411 to 413 are connected to the diffusion layer regions 221, 223 and 225, and the accumulated electric charge is converted into voltage and is output to output terminals VOUT1 to VOUT3 as analog signals. A scan-in terminal Sin is connected to a diffusion layer region 220, and a scan-out terminal Sout is connected to the diffusion layer region 225 via an electric charge/voltage conversion amplifier 401.

Abstract: A digital-to-analog convertor divides an input digital signal into a least significant bit group and a most significant bit group. The most significant bit group is converted using pulse amplitude modulation and the least significant bit group is converted using pulse width modulation, in which the pulse widths are varied symmetrically about predetermined time points within a conversion period in order to improve the linearity of the pulse width modulation conversion.

Abstract: An analog-to-digital or digital-to-analog converter comprises: a signal input terminal an integrator connected to the signal input terminal; a plurality of constant current sources connected to the integrator so that the integrator is supplied with respective constant currents; a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; and a clock signal generator for generating a first clock signal having a first clock frequency and being supplied to the first counter and a second clock signal having a second frequency higher than the first clock frequency and being supplied to the second counter; and currents of the plurality of constant current sources are respectively determined according to the first and second predetermined numbers of bits and the first and second clock frequencies of the first and second clock signals, respectively.

Abstract: An integrating digital-to-analog converter circuit includes an operational-amplifier based integrator, a plurality of constant current sources each providing constant current at a respective different level, and a plurality of switches each associated with a respective current source for coupling the same to the integrator. A plurality of digital counters are arranged to hold a predetermined portion of an n-bit digital word loaded therein and to count clock pulses until their contents reach a predetermined count. At those times, a carry pulse is generated in each such digital counter and the associated switch is opened to cut off the associated current source. Such a digital-to-analog converter circuit can convert data words of relatively high bit length without the need for an excessively high frequency clocking signal.