Patents by Inventor Ikuto Fukuoka
Ikuto Fukuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8503234Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.Type: GrantFiled: July 22, 2011Date of Patent: August 6, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
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Patent number: 8400828Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.Type: GrantFiled: March 30, 2012Date of Patent: March 19, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
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Publication number: 20120195121Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.Type: ApplicationFiled: March 30, 2012Publication date: August 2, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
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Publication number: 20110280072Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.Type: ApplicationFiled: July 22, 2011Publication date: November 17, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
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Patent number: 8014198Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.Type: GrantFiled: March 26, 2009Date of Patent: September 6, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
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Patent number: 7773425Abstract: A nonvolatile semiconductor memory that improved a read rate. In a memory cell array in which each memory cell includes two storage areas, thresholds of outer storage areas of two memory cells which are symmetrical with respect to two adjacent bit lines are set so as to create a pair relation between them. A word line selection circuit applies read voltage to a word line to which the two memory cells to be read are connected. A bit line selection circuit applies ground voltage to two bit lines just outside the two memory cells and applies predetermined read voltage to two bit lines inside the two memory cells. A read conversion circuit compares drain currents which run through the two memory cells activated by the word line selection circuit and the bit line selection circuit, and converts the drain currents into data.Type: GrantFiled: September 28, 2007Date of Patent: August 10, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Motoi Takahashi, Ikuto Fukuoka
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Publication number: 20090180320Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.Type: ApplicationFiled: March 26, 2009Publication date: July 16, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
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Publication number: 20080037329Abstract: A nonvolatile semiconductor memory that improved a read rate. In a memory cell array in which each memory cell includes two storage areas, thresholds of outer storage areas of two memory cells which are symmetrical with respect to two adjacent bit lines are set so as to create a pair relation between them. A word line selection circuit applies read voltage to a word line to which the two memory cells to be read are connected. A bit line selection circuit applies ground voltage to two bit lines just outside the two memory cells and applies predetermined read voltage to two bit lines inside the two memory cells. A read conversion circuit compares drain currents which run through the two memory cells activated by the word line selection circuit and the bit line selection circuit, and converts the drain currents into data.Type: ApplicationFiled: September 28, 2007Publication date: February 14, 2008Inventors: Motoi Takahashi, Ikuto Fukuoka
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Patent number: 7307892Abstract: A function switching part has a pair of programming elements programmed to different logic values. A decision circuit in the function switching part outputs a logic level according to a difference between the currents flowing in the programming elements, while the power supply voltage rises at the power-on. The operating specification of an option functional part is switched according to the logic level output from the decision circuit. That is, the operating specification of the option functional part is automatically decided according to the program state of the programming element before the power-on operation is completed. The read operation for the programming element need not be performed for deciding the operating specification of the option functional part. Since the initial process after the power-on period is simplified, the period from when the power is turned on to when the normal operation begins can be shortened.Type: GrantFiled: February 23, 2006Date of Patent: December 11, 2007Assignee: Fujitsu LimitedInventors: Motoi Takahashi, Ikuto Fukuoka
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Patent number: 7209340Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and fType: GrantFiled: September 18, 2006Date of Patent: April 24, 2007Assignee: Fujitsu LimitedInventors: Osamu Iioka, Ikuto Fukuoka
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Publication number: 20070013029Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and fType: ApplicationFiled: September 18, 2006Publication date: January 18, 2007Applicant: FUJITSU LIMITEDInventors: Osamu Iioka, Ikuto Fukuoka
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Patent number: 7139194Abstract: Each nonvolatile memory cell transistor has such directivities that a current flows only from the drain to the source and that charge is exchangeable only at the source. The source of one of a pair of memory cell transistors connected to each word line is connected to the drain of the other memory cell transistor, and the drain of the one memory cell transistor is connected to the source of the other. During a data rewrite operation, reverse voltages are applied to the sources and drains of the pair of memory cell transistors. Because of the directivities of each memory cell transistor, charge is exchanged with a charge accumulation layer only in the source region. This makes the data rewritable in only one of the pair of memory cell transistors. As a result, data is rewritable on a memory cell basis without increasing the memory cell size.Type: GrantFiled: June 29, 2005Date of Patent: November 21, 2006Assignee: Fujitsu LimitedInventor: Ikuto Fukuoka
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Patent number: 7126809Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and fType: GrantFiled: June 22, 2005Date of Patent: October 24, 2006Assignee: Fujitsu LimitedInventors: Osamu Iioka, Ikuto Fukuoka
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Publication number: 20060221716Abstract: A function switching part has a pair of programming elements programmed to different logic values. A decision circuit in the function switching part outputs a logic level according to a difference between the currents flowing in the programming elements, while the power supply voltage rises at the power-on. The operating specification of an option functional part is switched according to the logic level output from the decision circuit. That is, the operating specification of the option functional part is automatically decided according to the program state of the programming element before the power-on operation is completed. The read operation for the programming element need not be performed for deciding the operating specification of the option functional part. Since the initial process after the power-on period is simplified, the period from when the power is turned on to when the normal operation begins can be shortened.Type: ApplicationFiled: February 23, 2006Publication date: October 5, 2006Inventors: Motoi Takahashi, Ikuto Fukuoka
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Publication number: 20060208339Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and fType: ApplicationFiled: June 22, 2005Publication date: September 21, 2006Applicant: FUJITSU LIMITEDInventors: Osamu Iioka, Ikuto Fukuoka
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Publication number: 20050237799Abstract: Each nonvolatile memory cell transistor has such directivities that a current flows only from the drain to the source and that charge is exchangeable only at the source. The source of one of a pair of memory cell transistors connected to each word line is connected to the drain of the other memory cell transistor, and the drain of the one memory cell transistor is connected to the source of the other. During a data rewrite operation, reverse voltages are applied to the sources and drains of the pair of memory cell transistors. Because of the directivities of each memory cell transistor, charge is exchanged with a charge accumulation layer only in the source region. This makes the data rewritable in only one of the pair of memory cell transistors. As a result, data is rewritable on a memory cell basis without increasing the memory cell size.Type: ApplicationFiled: June 29, 2005Publication date: October 27, 2005Inventor: Ikuto Fukuoka
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Publication number: 20020001230Abstract: According to the present invention, the above-described objects can be achieved by a semiconductor storage device including: memory cells for storing data by accumulating or not accumulating charges, such as electrons, into floating gate; wherein the memory cell includes first memory cells having first charge exchange capability with respect to a charge exchange for the floating gate, and second memory cells having second charge exchange capability, so that data to be returned can be stored. In the semiconductor storage device according to the present invention, when all erase or all write (program) is performed to the memory cells, the first memory cells become to have a different threshold voltage from the second memory cells according to the different charge exchange capability of the memory cells, thus data to be returned can be read out.Type: ApplicationFiled: June 7, 1999Publication date: January 3, 2002Inventor: IKUTO FUKUOKA
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Non-volatile semiconductor memory including memory cells having different charge exchange capability
Patent number: 6327186Abstract: According to the present invention, the above-described objects can be achieved by a semiconductor storage device including: memory cells for storing data by accumulating or not accumulating charges, such as electrons, into floating gate; wherein the memory cell includes first memory cells having first charge exchange capability with respect to a charge exchange for the floating gate, and second memory cells having second charge exchange capability, so that data to be returned can be stored. In the semiconductor storage device according to the present invention, when all erase or all write (program) is performed to the memory cells, the first memory cells become to have a different threshold voltage from the second memory cells according to the different charge exchange capability of the memory cells, thus data to be returned can be read out.Type: GrantFiled: June 7, 1999Date of Patent: December 4, 2001Assignee: Fujitsu LimitedInventor: Ikuto Fukuoka