Patents by Inventor Ikuya Ono

Ikuya Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7454176
    Abstract: The present invention provides a semiconductor integrated circuit for communication (RF IC) operable in a mode for receiving a received signal subjected to phase modulation and amplitude modulation and a mode for receiving a received signal subjected only to phase modulation. In the semiconductor integrated circuit for communication, a frequency band of a loop filter in a PLL circuit is switched and set so as to become large in a reception mode and become small in a transmission mode.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiya Uozumi, Ikuya Ono, Jiro Shinbo
  • Publication number: 20070202814
    Abstract: A receiving circuit of a direct conversion system which includes a differential amplifier circuit which amplifies a received signal, a mixer which combines the amplified received signal and an oscillation signal having a predetermined frequency to perform frequency conversion, and a high gain amplifier circuit in which programmable gain amplifiers and filters which eliminate noise of the received signal, are connected in a multistage and which is configured such that an amplification factor is varied according to the level of the received signal. In the receiving circuit, the low noise amplifier is brought to a non-operating state to allow execution of a DC offset cancel operation of the programmable gain amplifier on the pre-stage side of the high gain amplifier circuit. Thereafter, the low noise amplifier is brought to an operating state to allow execution of a DC offset cancel operation of the final-stage programmable gain amplifier.
    Type: Application
    Filed: April 27, 2007
    Publication date: August 30, 2007
    Inventors: Ikuya Ono, Tamotsu Takahashi
  • Publication number: 20070202813
    Abstract: A receiving circuit of a direct conversion system which includes a differential amplifier circuit which amplifies a received signal, a mixer which combines the amplified received signal and an oscillation signal having a predetermined frequency to perform frequency conversion, and a high gain amplifier circuit in which programmable gain amplifiers and filters which eliminate noise of the received signal, are connected in a multistage and which is configured such that an amplification factor is varied according to the level of the received signal. In the receiving circuit, the low noise amplifier is brought to a non-operating state to allow execution of a DC offset cancel operation of the programmable gain amplifier on the pre-stage side of the high gain amplifier circuit. Thereafter, the low noise amplifier is brought to an operating state to allow execution of a DC offset cancel operation of the final-stage programmable gain amplifier.
    Type: Application
    Filed: April 27, 2007
    Publication date: August 30, 2007
    Inventors: Ikuya Ono, Tamotsu Takahashi
  • Patent number: 7257385
    Abstract: A receiving circuit of a direct conversion system is provided which includes a differential amplifier circuit which amplifies a received signal, a mixer which combines the amplified received signal and an oscillation signal having a predetermined frequency to thereby perform frequency conversion, and a high gain amplifier circuit in which a plurality of programmable gain amplifiers and a plurality of filters which eliminate noise of the received signal and an unnecessary wave, are connected in a multistage and which is configured such that an amplification factor is varied according to the level of the received signal. In the receiving circuit, the low noise amplifier is brought to a non-operating state to thereby allow execution of a DC offset cancel operation of the corresponding programmable gain amplifier on the pre-stage side of the high gain amplifier circuit.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 14, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Ikuya Ono, Tamotsu Takahashi
  • Publication number: 20070126083
    Abstract: The semiconductor device provided assures stable communication processes. For example, a varactor diode for adjusting the reference frequency is comprised within a digital crystal-controlled oscillating circuit provided as an internal circuit of the front-end circuit for generating the reference oscillation signal of a PLL circuit or the like. The varactor diode is formed to a semiconductor layer DF of the so-called SOI structure in the structure where an embedded insulating layer, a n?type semiconductor region, a p type semiconductor region, and a n+ type semiconductor region are formed in this sequence and the n+ type semiconductor region is connected to a cathode node which becomes the frequency adjusting node. Moreover, a p+ type semiconductor region connected to the p type semiconductor region is formed in both sides of the n+ type semiconductor region, and this p+ type semiconductor region is connected to an anode node to which the ground voltage is applied.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 7, 2007
    Inventors: Kentaro SUZUKI, Ikuya Ono, Tadatoshi Danno
  • Publication number: 20060211390
    Abstract: The present invention provides a semiconductor integrated circuit for communication (RF IC) operable in a mode for receiving a received signal subjected to phase modulation and amplitude modulation and a mode for receiving a received signal subjected only to phase modulation. In the semiconductor integrated circuit for communication, a frequency band of a loop filter in a PLL circuit is switched and set so as to become large in a reception mode and become small in a transmission mode.
    Type: Application
    Filed: February 24, 2006
    Publication date: September 21, 2006
    Inventors: Toshiya Uozumi, Ikuya Ono, Jiro Shinbo
  • Patent number: 7050779
    Abstract: The thermal interference due to the self heating of transistors constituting a gilbert cell circuit is reduced, thereby largely improving the receiving sensitivity to signals. A mixer circuit composed of a gilbert cell circuit comprises transistors T1 to T6. Each of the transistors T1 to T4 is con figured so that four transistors may be connected in parallel. In a layout on a semiconductor chip, four transistors T1a to T1d and T2a to T2d respectively constituting the transistors T1 and T2 are respectively separated into two pairs, and the respective two pairs are laid out in a crisscross shape so that they are crossed with each other. Similarly, four transistors T3a to T3d and T4a to T4d respectively constituting the transistors T3 and T4 are respectively separated into two pairs, and the respective two pairs are laid out in a crisscross shape so that they are crossed with each other. Thus, the thermal influence applied on the transistors T1 to T4 is uniformed.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: May 23, 2006
    Assignees: Hitachi, Ltd., Akita Electronics Systems Co., Ltd.
    Inventors: Ikuya Ono, Kazuhiro Tagawa, Satoru Takahashi
  • Publication number: 20050075088
    Abstract: A receiving circuit of a direct conversion system is provided which includes a differential amplifier circuit which amplifies a received signal, a mixer which combines the amplified received signal and an oscillation signal having a predetermined frequency to thereby perform frequency conversion, and a high gain amplifier circuit in which a plurality of programmable gain amplifiers and a plurality of filters which eliminate noise of the received signal and an unnecessary wave, are connected in a multistage and which is configured such that an amplification factor is varied according to the level of the received signal. In the receiving circuit, the low noise amplifier is brought to a non-operating state to thereby allow execution of a DC offset cancel operation of the corresponding programmable gain amplifier on the pre-stage side of the high gain amplifier circuit.
    Type: Application
    Filed: September 24, 2004
    Publication date: April 7, 2005
    Inventors: Ikuya Ono, Tamotsu Takahashi
  • Publication number: 20040180643
    Abstract: The thermal interference due to the self heating of transistors constituting a gilbert cell circuit is reduced, thereby largely improving the receiving sensitivity to signals. A mixer circuit composed of a gilbert cell circuit comprises transistors T1 to T6. Each of the transistors T1 to T4 is configured so that four transistors may be connected in parallel. In a layout on a semiconductor chip, four transistors T1a to T1d and T2a to T2d respectively constituting the transistors T1 and T2 are respectively separated into two pairs, and the respective two pairs are laid out in a crisscross shape so that they are crossed with each other. Similarly, four transistors T3a to T3d and T4a to T4d respectively constituting the transistors T3 and T4 are respectively separated into two pairs, and the respective two pairs are laid out in a crisscross shape so that they are crossed with each other. Thus, the thermal influence applied on the transistors T1 to T4 is uniformed.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 16, 2004
    Inventors: Ikuya Ono, Kazuhiro Tagawa, Satoru Takahashi