Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.

Abstract: Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

Abstract: Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.

Abstract: Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

Abstract: A method for fabricating a dual poly gate in a semiconductor device, comprising: forming a gate insulation layer and a polysilicon layer on a semiconductor substrate that defines a first region and a second region; implanting first and second conductive type impurity ions into the first region and the second region of the polysilicon layer, respectively; forming first and second conductive type polysilicon layer in the first and second regions, respectively, by annealing the semiconductor substrate; forming a barrier metal layer on the first and second conductive type polysilicon layers; forming an oxide layer that lowers resistance of a metal by an oxidation process; forming a metal layer and a hard mask layer on the oxide layer; and forming a first conductive type poly gate on the first region and a second conductive type poly gate on the second region by a patterning process.

Abstract: In one embodiment, a semiconductor device may includes a through via disposed within a substrate with a diffusion barrier layer disposed over the through via and the substrate. An insulation layer may be disposed over the diffusion barrier layer, a metal interconnection layer disposed within the insulation layer over at least a portion of the via contact, and a via contact disposed between the metal interconnection layer and the through via within the insulation layer. The via contact may have a cross-sectional area larger than a cross-sectional area of the through via so that the through via and the diffusion barrier layer do not contact each other.

Abstract: Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber.

Abstract: A method for fabricating a dual poly gate in a semiconductor device, comprising: forming a gate insulation layer and a polysilicon layer on a semiconductor substrate that defines a first region and a second region; implanting first and second conductive type impurity ions into the first region and the second region of the polysilicon layer, respectively; forming first and second conductive type polysilicon layer in the first and second regions, respectively, by annealing the semiconductor substrate; forming a barrier metal layer on the first and second conductive type polysilicon layers; forming an oxide layer that lowers resistance of a metal by an oxidation process; forming a metal layer and a hard mask layer on the oxide layer; and forming a first conductive type poly gate on the first region and a second conductive type poly gate on the second region by a patterning process.

Abstract: Disclosed herein are a method of forming a stable phase change layer without generating seams, and a method of manufacturing phase change memory device using the same. In the method of forming a phase change layer, the phase change layer is formed by performing a first deposition process of a phase change material, performing an etching process so as to etch the phase change material, and performing a second deposition process of a phase change material on the etched phase change material. The etching process and the second deposition process are performed a predetermined number of times.

Abstract: Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber.