Patents by Inventor Il-Goo Kim
Il-Goo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11810853Abstract: The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.Type: GrantFiled: March 23, 2022Date of Patent: November 7, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Il Goo Kim, Roderick A. Augur
-
Patent number: 11502087Abstract: A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor device comprises: a first active region over a substrate; and a first bit line structure intercepting the first active region at a level that is lower than a top-most surface thereof, the first bit line structure including a barrier liner having a U-profile in a width direction thereof in electrical contact with the first active region.Type: GrantFiled: January 21, 2020Date of Patent: November 15, 2022Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.Inventor: Il-Goo Kim
-
Patent number: 11423951Abstract: A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure comprises an active region over a substrate defining a top surface and a gate structure embedded in the active region. In a cross section of the active region, the gate structure includes a conductive feature having a first width buried in the active region and reaching a first depth therein; an insulating cap having a second width arranged above the conductive feature in the active region and reaching a second depth therein; and a dielectric liner arranged between the active region and the conductive feature. The first width is smaller than the second width.Type: GrantFiled: January 12, 2020Date of Patent: August 23, 2022Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.Inventor: Il-Goo Kim
-
Publication number: 20220216148Abstract: The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.Type: ApplicationFiled: March 23, 2022Publication date: July 7, 2022Inventors: Il Goo KIM, Roderick A. AUGUR
-
Patent number: 11315870Abstract: The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.Type: GrantFiled: November 21, 2018Date of Patent: April 26, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Il Goo Kim, Roderick A. Augur
-
Publication number: 20210225849Abstract: A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor device comprises: a first active region over a substrate; and a first bit line structure intercepting the first active region at a level that is lower than a top-most surface thereof, the first bit line structure including a barrier liner having a U-profile in a width direction thereof in electrical contact with the first active region.Type: ApplicationFiled: January 21, 2020Publication date: July 22, 2021Inventor: IL-GOO KIM
-
Publication number: 20210217447Abstract: A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure comprises an active region over a substrate defining a top surface and a gate structure embedded in the active region. In a cross section of the active region, the gate structure includes a conductive feature having a first width buried in the active region and reaching a first depth therein; an insulating cap having a second width arranged above the conductive feature in the active region and reaching a second depth therein; and a dielectric liner arranged between the active region and the conductive feature. The first width is smaller than the second width.Type: ApplicationFiled: January 12, 2020Publication date: July 15, 2021Inventor: IL-GOO KIM
-
Publication number: 20200161236Abstract: The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.Type: ApplicationFiled: November 21, 2018Publication date: May 21, 2020Inventors: Il Goo KIM, Roderick A. AUGUR
-
Patent number: 8835328Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.Type: GrantFiled: February 8, 2013Date of Patent: September 16, 2014Assignee: Globalfoundries, Inc.Inventors: Wontae Hwang, Il Goo Kim, Dae-Han Choi, Sang Cheol Han
-
Publication number: 20140227879Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Wontae Hwang, IL Goo Kim, DAE-HAN Choi, Sang Cheol Han
-
Patent number: 7560332Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: GrantFiled: April 10, 2007Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Woo Lee, Wan-Jae Park, Jeong-Hoon Ahn, Kyung-Tae Lee, Mu-Kyeng Jung, Yong-Jun Lee, Il-Goo Kim, Soo-Geun Lee
-
Patent number: 7553761Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a low-k dielectric layer on a semiconductor substrate, forming a mask pattern on the low-k dielectric layer, and dry etching the low-k dielectric layer using the mask pattern as an etch mask. A dry etching gas is used for the dry etching of the low-k dielectric layer. The dry etching gas includes a mixture of a gas containing chlorine atoms and at least one gas selected from a group consisting of a gas containing oxygen atoms, a gas containing nitrogen atoms, and an inert gas. The dry etching gas does not contain fluorine atoms.Type: GrantFiled: January 4, 2006Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Il-Goo Kim, Ju-Hyuck Chung
-
Publication number: 20080124917Abstract: In a method of manufacturing a semiconductor device having air gaps, an organic sacrificial layer pattern is formed on a semiconductor substrate, wherein the organic sacrificial layer pattern includes openings. Metal structures are formed in the openings. The organic sacrificial layer pattern is removed by a plasma ashing treatment using a source gas including oxygen (O2) and carbon monoxide (CO). An insulating interlayer is formed to have air gaps between the metal structures. Resistance-capacitance (RC) delay and crosstalk between the metal structures may be efficiently suppressed.Type: ApplicationFiled: November 20, 2007Publication date: May 29, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-Hwan Oh, Ju-Hyuck Chung, Il-Goo Kim, Hyoung-Sik Kim
-
Publication number: 20080073787Abstract: A metal (e.g., copper) interconnect and related method of fabrication are disclosed in which the metal interconnect is formed by electro-plating a seed layer formed on a recess in a substrate before a metal layer is electro-plated to fill the recess.Type: ApplicationFiled: January 19, 2007Publication date: March 27, 2008Inventors: Jun-Hwan Oh, Hyoung-Sik Kim, Il-Goo Kim, Ju-Hyuck Chung
-
Publication number: 20070184610Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: ApplicationFiled: April 10, 2007Publication date: August 9, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-woo Lee, Wan-jae Park, Jeong-hoon Ahn, Kyung-tae Lee, Mu-kyeng Jung, Yong-jun Lee, Il-goo Kim, Soo-geun Lee
-
Patent number: 7229875Abstract: Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: GrantFiled: October 16, 2003Date of Patent: June 12, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Wan-jae Park, Jeong-hoon Ahn, Kyung-tae Lee, Mu-kyeng Jung, Yong-jun Lee, Il-goo Kim, Soo-geun Lee
-
Patent number: 7176126Abstract: In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.Type: GrantFiled: June 21, 2005Date of Patent: February 13, 2007Assignee: Samsung Electronics, Co., Ltd.Inventors: Hyeok-sang Oh, Ju-hyuck Chung, Il-goo Kim
-
Patent number: 7157366Abstract: Various methods are provided for forming metal interconnection layers of semiconductor devices.Type: GrantFiled: July 9, 2004Date of Patent: January 2, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Il-Goo Kim, Sang-Rok Hah, Sae-il Son, Kyoung-Woo Lee
-
Publication number: 20060148264Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a low-k dielectric layer on a semiconductor substrate, forming a mask pattern on the low-k dielectric layer, and dry etching the low-k dielectric layer using the mask pattern as an etch mask. A dry etching gas is used for the dry etching of the low-k dielectric layer. The dry etching gas includes a mixture of a gas containing chlorine atoms and at least one gas selected from a group consisting of a gas containing oxygen atoms, a gas containing nitrogen atoms, and an inert gas. The dry etching gas does not contain fluorine atoms.Type: ApplicationFiled: January 4, 2006Publication date: July 6, 2006Inventors: Il-Goo Kim, Ju-Hyuck Chung
-
Patent number: 7033944Abstract: A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.Type: GrantFiled: September 4, 2003Date of Patent: April 25, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Wan-Jae Park, Il-Goo Kim, Sang-Rok Hah, Kyoung-Woo Lee