Patents by Inventor IL GYOU SHIN
IL GYOU SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096954Abstract: A semiconductor device includes an active pattern including: a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; a gate structure on the lower pattern and including a gate electrode and a gate insulating film including an interfacial insulating film including a first vertical portion and a horizontal portion. A dimension in a third direction of the first vertical portion is greater than a dimension in the second direction of the horizontal portion. The first vertical portion includes: a first area contacting a source/drain pattern; and a second area provided between the first area and the gate electrode. The interfacial insulating film includes a first element other than silicon, wherein a concentration of the first element in the first area is greater than a concentration of the first element in the second area.Type: ApplicationFiled: August 8, 2023Publication date: March 21, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il Gyou SHIN, Hyun Ho NOH, Sang Yong KIM, You Bin KIM
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Patent number: 11735663Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.Type: GrantFiled: December 30, 2021Date of Patent: August 22, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Bum Kim, Gyeom Kim, Da Hye Kim, Jae Mun Kim, Il Gyou Shin, Seung Hun Lee, Kyung In Choi
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Publication number: 20220123145Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.Type: ApplicationFiled: December 30, 2021Publication date: April 21, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jin Bum KIM, Gyeom KIM, Da Hye KIM, Jae Mun KIM, Il Gyou SHIN, Seung Hun LEE, Kyung In CHOI
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Patent number: 11233150Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.Type: GrantFiled: June 24, 2020Date of Patent: January 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Bum Kim, Gyeom Kim, Da Hye Kim, Jae Mun Kim, Il Gyou Shin, Seung Hun Lee, Kyung In Choi
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Publication number: 20210098626Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.Type: ApplicationFiled: June 24, 2020Publication date: April 1, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jin Bum KIM, Gyeom KIM, Da Hye KIM, Jae Mun KIM, Il Gyou SHIN, Seung Hun LEE, Kyung In CHOI
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Patent number: 10727025Abstract: A system of analyzing a crystal defect includes an image processor, an image generator, and a comparator. The image processor processes a measured transmission electron microscope (TEM) image that is provided by capturing an image of a specimen having a crystal structure, to provide structural defect information of the specimen. The image generator provides a plurality of virtual TEM images corresponding to a plurality of three-dimensional structural defects of the crystal structure. The comparator compares the measured TEM image with the plurality of virtual TEM images using the structural defect information to determine a defect type of the measured TEM image.Type: GrantFiled: January 25, 2019Date of Patent: July 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Bo Shim, Il-Gyou Shin, Seon-Young Lee, Alexander Schmidt, Shin-Wook Yi
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Publication number: 20200020506Abstract: A system of analyzing a crystal defect includes an image processor, an image generator, and a comparator. The image processor processes a measured transmission electron microscope (TEM) image that is provided by capturing an image of a specimen having a crystal structure, to provide structural defect information of the specimen. The image generator provides a plurality of virtual TEM images corresponding to a plurality of three-dimensional structural defects of the crystal structure. The comparator compares the measured TEM image with the plurality of virtual TEM images using the structural defect information to determine a defect type of the measured TEM image.Type: ApplicationFiled: January 25, 2019Publication date: January 16, 2020Inventors: Sung-Bo Shim, Il-Gyou Shin, Seon-Young Lee, Alexander Schmidt, Shin-Wook Yi
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Patent number: 10504992Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.Type: GrantFiled: September 26, 2017Date of Patent: December 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Hoon Kim, Hyun Jung Lee, Kyung Hee Kim, Sun Jung Kim, Jin Bum Kim, Il Gyou Shin, Seung Hun Lee, Cho Eun Lee, Dong Suk Shin
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Patent number: 10128112Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.Type: GrantFiled: May 16, 2017Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cho Eun Lee, Jin Bum Kim, Kang Hun Moon, Jae Myung Choe, Sun Jung Kim, Dong Suk Shin, Il Gyou Shin, Jeong Ho Yoo
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Publication number: 20180138269Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.Type: ApplicationFiled: September 26, 2017Publication date: May 17, 2018Inventors: Seok Hoon KIM, Hyun Jung LEE, Kyung Hee KIM, Sun Jung KIM, Jin Bum KIM, Il Gyou SHIN, Seung Hun LEE, Cho Eun LEE, Dong Suk SHIN
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Publication number: 20180096845Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.Type: ApplicationFiled: May 16, 2017Publication date: April 5, 2018Inventors: Cho Eun LEE, Jin Bum KIM, Kang Hun MOON, Jae Myung CHOE, Sun Jung KIM, Dong Suk SHIN, IL GYOU SHIN, Jeong Ho YOO