Patents by Inventor Il Jung Kim
Il Jung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948883Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.Type: GrantFiled: April 2, 2021Date of Patent: April 2, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seonghun Lim, Wookyung You, Kyoungwoo Lee, Juyoung Jung, Il Sup Kim, Chin Kim, Kyoungpil Park, Jinhyung Park
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Patent number: 11941219Abstract: A touch sensor includes a base layer including a sensing area and a non-sensing area; and a sensor electrode disposed in the sensing area and including sensor patterns. The sensing area may include a first area including at least one non-square boundary with a predetermined curvature and a second area not including the non-square boundary. In an exemplary embodiment of the present inventive concept, sensor patterns disposed in the first area and sensor patterns disposed in the second area among the sensor patterns may have different sizes from each other.Type: GrantFiled: November 12, 2021Date of Patent: March 26, 2024Assignee: Samsung Display Co., Ltd.Inventors: Won Jun Choi, Il Joo Kim, Deok Jung Kim
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Patent number: 11923480Abstract: A light-emitting device and a display device using the same are disclosed. The light-emitting device improves the reliability of a process of disposing light-emitting devices. The light-emitting device is configured to ensure electrical connections even if the light-emitting device is inverted while being disposed on a substrate. The light-emitting device includes an n-type semiconductor layer and a p-type semiconductor layer. N-type electrodes and p-type electrodes are disposed on both sides of top and bottom surfaces of the light-emitting device. Contact holes are provided to electrically connect one of the n-type electrodes to the n-type semiconductor layer and one of the p-type electrodes to the p-type semiconductor layer. When the light-emitting device is inverted while being disposed on a substrate, the light-emitting device operates ordinarily, thereby reducing the defect rate of a display device.Type: GrantFiled: March 17, 2022Date of Patent: March 5, 2024Assignee: LG DISPLAY CO., LTD.Inventors: Taeil Jung, Il-Soo Kim, YongSeok Kwak
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Publication number: 20230096947Abstract: According to an embodiment, in a solution provision method and system: a target solution for a target factory is determined in a platform in which solutions for a smart factory, the solutions including at least one template, are registered; at least one target template corresponding to the target solution is revised according to an environment of the target factory; and the target solution, to which the revised target template is applied, is applied to the target factory.Type: ApplicationFiled: June 5, 2020Publication date: March 30, 2023Applicants: Korea Advanced Institute of Science and Technology, Aim System, Inc.Inventors: Heung Nam Kim, Jae Hoon Kim, Il Jung Kim, Hee Su Chae, Man Ki Kim, Sung Joon Byun, Byoung Hoon Jang
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Patent number: 9213971Abstract: Pre-purchase and post-purchase item information provision methods and systems using an RFID technology and computer readable storage media storing programs for executing the methods are provided.Type: GrantFiled: February 7, 2008Date of Patent: December 15, 2015Assignee: KOREA UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATIONInventors: Dong Hoon Lee, Eun Young Choi, Il Jung Kim
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Publication number: 20080208753Abstract: Pre-purchase and post-purchase item information provision methods and systems using an RFID technology and computer readable storage media storing programs for executing the methods are provided.Type: ApplicationFiled: February 7, 2008Publication date: August 28, 2008Inventors: Dong Hoon Lee, Eun Young Choi, Il Jung Kim
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Patent number: 7321152Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: August 4, 2006Date of Patent: January 22, 2008Assignee: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Patent number: 7187040Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: March 14, 2005Date of Patent: March 6, 2007Assignee: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Publication number: 20060267012Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: ApplicationFiled: August 4, 2006Publication date: November 30, 2006Applicant: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Patent number: 7112854Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: May 2, 1997Date of Patent: September 26, 2006Assignee: Renesas Technology CorporationInventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Publication number: 20050167673Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: ApplicationFiled: March 14, 2005Publication date: August 4, 2005Applicant: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Patent number: 6310377Abstract: FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.Type: GrantFiled: August 17, 1998Date of Patent: October 30, 2001Inventors: Shigenobu Maeda, Yasuo Yamaguchi, Il Jung Kim, Yasuo Inoue, Shigeto Maegawa, Takashi Ipposhi
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Patent number: 5808341Abstract: FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.Type: GrantFiled: November 12, 1996Date of Patent: September 15, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigenobu Maeda, Yasuo Yamaguchi, Il Jung Kim, Yasuo Inoue, Shigeto Maegawa, Takashi Ipposhi