Patents by Inventor Il Jung Kim

Il Jung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12321877
    Abstract: According to an embodiment, in a solution provision method and system: a target solution for a target factory is determined in a platform in which solutions for a smart factory, the solutions including at least one template, are registered; at least one target template corresponding to the target solution is revised according to an environment of the target factory; and the target solution, to which the revised target template is applied, is applied to the target factory.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: June 3, 2025
    Assignees: Korea Advanced Institute of Science and Technology, Aim System, Inc.
    Inventors: Heung Nam Kim, Jae Hoon Kim, Il Jung Kim, Hee Su Chae, Man Ki Kim, Sung Joon Byun, Byoung Hoon Jang
  • Publication number: 20230096947
    Abstract: According to an embodiment, in a solution provision method and system: a target solution for a target factory is determined in a platform in which solutions for a smart factory, the solutions including at least one template, are registered; at least one target template corresponding to the target solution is revised according to an environment of the target factory; and the target solution, to which the revised target template is applied, is applied to the target factory.
    Type: Application
    Filed: June 5, 2020
    Publication date: March 30, 2023
    Applicants: Korea Advanced Institute of Science and Technology, Aim System, Inc.
    Inventors: Heung Nam Kim, Jae Hoon Kim, Il Jung Kim, Hee Su Chae, Man Ki Kim, Sung Joon Byun, Byoung Hoon Jang
  • Patent number: 9213971
    Abstract: Pre-purchase and post-purchase item information provision methods and systems using an RFID technology and computer readable storage media storing programs for executing the methods are provided.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: December 15, 2015
    Assignee: KOREA UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATION
    Inventors: Dong Hoon Lee, Eun Young Choi, Il Jung Kim
  • Publication number: 20080208753
    Abstract: Pre-purchase and post-purchase item information provision methods and systems using an RFID technology and computer readable storage media storing programs for executing the methods are provided.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 28, 2008
    Inventors: Dong Hoon Lee, Eun Young Choi, Il Jung Kim
  • Patent number: 7321152
    Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: January 22, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
  • Patent number: 7187040
    Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: March 6, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
  • Publication number: 20060267012
    Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
  • Patent number: 7112854
    Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: September 26, 2006
    Assignee: Renesas Technology Corporation
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
  • Publication number: 20050167673
    Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
    Type: Application
    Filed: March 14, 2005
    Publication date: August 4, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
  • Patent number: 6310377
    Abstract: FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.
    Type: Grant
    Filed: August 17, 1998
    Date of Patent: October 30, 2001
    Inventors: Shigenobu Maeda, Yasuo Yamaguchi, Il Jung Kim, Yasuo Inoue, Shigeto Maegawa, Takashi Ipposhi
  • Patent number: 5808341
    Abstract: FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: September 15, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigenobu Maeda, Yasuo Yamaguchi, Il Jung Kim, Yasuo Inoue, Shigeto Maegawa, Takashi Ipposhi