Patents by Inventor Il Kwon Shim

Il Kwon Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240339484
    Abstract: A semiconductor device has a substrate. A semiconductor die with a photosensitive circuit is disposed over the substrate. A lens comprising a protective layer is disposed over the photosensitive circuit. An encapsulant is deposited over the substrate, semiconductor die, and lens. The protective layer is removed after depositing the encapsulant.
    Type: Application
    Filed: June 19, 2024
    Publication date: October 10, 2024
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: IL Kwon Shim, Jeffrey Punzalan
  • Patent number: 12100719
    Abstract: A semiconductor package and method for forming thereof are disclosed. The package includes a package substrate having a die region with a die attached thereto. An encapsulant is disposed to cover encapsulation region of the package substrate. A protective cover is disposed over the die and attached to the encapsulant by a cover adhesive. The protective cover is supported by a lower portion of step shaped inner encapsulant sidewalls.
    Type: Grant
    Filed: June 20, 2021
    Date of Patent: September 24, 2024
    Assignee: UTAC Headquarters Pte Ltd.
    Inventors: Jeffrey Punzalan, Il Kwon Shim
  • Publication number: 20240186346
    Abstract: A semiconductor package for a sensor is disclosed. The package includes an opaque layer on the encapsulation to prevent the wire bonds encased by the encapsulation from being visible to the naked eye. This reduces or prevents reflectance which improves the performance of the sensor. In some cases, the opaque layer extends beyond the encapsulation to cover a peripheral portion of the cover to form a cover opaque region. The cover opaque region reduces or prevents flaring and scattering of light, further enhancing the performance of the sensor.
    Type: Application
    Filed: November 22, 2023
    Publication date: June 6, 2024
    Inventors: Jeffrey Punzalan, Catherine Cheh Yee Chang, Il Kwon Shim
  • Patent number: 11961764
    Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: April 16, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
  • Patent number: 11901308
    Abstract: The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: February 13, 2024
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Il Kwon Shim, Kok Chuen Lock, Roel Adeva Robles, Eakkasit Dumsong
  • Patent number: 11881494
    Abstract: A semiconductor package and a method of manufacturing thereof is disclosed. The package includes a package substrate having a die attach region with a die attached thereto. A protective cover is disposed over a sensor region of the die and attached to the die by a cover adhesive. The package includes a dam structure configured to protect components of the semiconductor package from contamination.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: January 23, 2024
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Jeffrey Punzalan, Il Kwon Shim
  • Patent number: 11842991
    Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: December 12, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, OhHan Kim, HeeSoo Lee, HunTeak Lee, InSang Yoon, Il Kwon Shim
  • Publication number: 20230343668
    Abstract: A semiconductor device has a substrate and a first insulating layer formed over a first major surface of the substrate. A first redistribution layer is formed over the first insulating layer. A second insulating layer is formed over the first redistribution layer. A second redistribution layer can be formed over the second insulating layer, and a third insulating layer can be formed over the second redistribution layer. A protection layer is formed over a second major surface of the substrate for warpage control. A conductive layer is formed over the first redistribution layer, and a bump is formed over the conductive layer. An under bump metallization can be formed under the bump. The protection layer extends over a side surface of the substrate between the first major surface and second major surface. The protection layer further extends over a side surface of the first insulating layer.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 26, 2023
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: Il Kwon Shim, Ronnie M. De Villa, Dzafir Bin Mohd Shariff
  • Publication number: 20230274979
    Abstract: Reliable plasma dicing of a processed wafer with a die attach film (DAF) attached to the bottom wafer surface to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer to serve as a dicing mask. Laser processing is employed to form a modified layer with cracks on a bottom portion of the wafer. Plasma dicing partially dices the processed wafer to about the modified layer. The dicing tape is expanded laterally away from the center of the partially diced processed wafer, singulating it into individual dies. Singulation of the partially plasma diced processed wafer is facilitated by the modified layer.
    Type: Application
    Filed: February 27, 2023
    Publication date: August 31, 2023
    Inventors: Dzafir Bin Mohd Shariff, Enrique E. Sarile, JR., Jackson Fernandez Rosario, Ronnie M. De Villa, Chan Loong Neo, Il Kwon Shim
  • Patent number: 11715703
    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: August 1, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: SungWon Cho, ChangOh Kim, Il Kwon Shim, InSang Yoon, KyoungHee Park
  • Publication number: 20230178413
    Abstract: Reliable plasma dicing of a wafer with a die attach film (DAF) to the bottom wafer surface to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer to serve as a dicing mask. A combination of plama dicing and laser cutting is employed. Plasma is employed to etch the wafer while laser is employed to cut the DAF.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 8, 2023
    Inventors: Dzafir Bin Mohd SHARIFF, IL KWON SHIM, Enrique E. SARILE, JR., Jackson Fernandez ROSARIO, Ronnie M. DE VILLA, Chan Loong NEO
  • Patent number: 11670521
    Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having a die attach region with a die attached thereto. A protective cover is disposed over a sensor region of the die and attached to the die by a cover adhesive. The protective cover is supported by a standoff structure disposed on the die and below the protective cover. An encapsulant is disposed to cover the package substrate while leaving the top package surface exposed.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: June 6, 2023
    Assignee: UTAC Headquarters Pte. Ltd
    Inventors: Il Kwon Shim, Jeffrey Punzalan
  • Publication number: 20230154795
    Abstract: The present disclosure relates to plasma dicing of wafer. More specifically, the present disclosure is directed to frame masks and methods for plasma dicing wafers utilizing frame masks. The frame mask includes a mask frame, wherein the mask frame includes a top ring mask support and a side ring mask support. A plurality of mask segments suspended from the top ring mask support by segment supports, the mask segments are configured to define dicing channels on a blank wafer. The frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing. The mask frame is configured to enable flow of plasma therethrough to the wafer to etch the wafer to form dicing channels defined by the mask segments.
    Type: Application
    Filed: November 11, 2022
    Publication date: May 18, 2023
    Inventors: Dzafir Bin Mohd Shariff, IL KWON SHIM, Enrique Jr Sarile, Jackson Fernandez Rosario, Ronnie M. De Villa, Chan Loong Neo
  • Publication number: 20230122384
    Abstract: A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a cover attached to the first major die surface, the cover includes top and bottom major cover surfaces and side cover surfaces.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 20, 2023
    Inventors: Il Kwon SHIM, Jeffrey PUNZALAN
  • Publication number: 20230098224
    Abstract: A semiconductor package is disclosed. The package includes a sensor die which is disposed on a package substrate. A cover structure is attached to a cover adhesive surrounding the sensor die, forming a cavity above the sensor die. The cover structure includes a primary cover structure and a secondary cover structure surrounding the primary cover structure. The secondary cover structure is configured to protect the primary cover structure from damage during packaging. The package also includes an encapsulant. The encapsulant covers side surfaces of the cover structure, sides of the cover adhesive, and exposed portions of the package substrate, leaving the first major cover surface exposed.
    Type: Application
    Filed: September 30, 2022
    Publication date: March 30, 2023
    Inventors: Il Kwon SHIM, Jeffrey PUNZALAN
  • Publication number: 20230036239
    Abstract: A semiconductor device has a substrate. A semiconductor die with a photosensitive circuit is disposed over the substrate. A lens comprising a protective layer is disposed over the photosensitive circuit. An encapsulant is deposited over the substrate, semiconductor die, and lens. The protective layer is removed after depositing the encapsulant.
    Type: Application
    Filed: July 25, 2022
    Publication date: February 2, 2023
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: Emmanuel Espiritu, Il Kwon Shim, Jeffrey Punzalan, Jose Mari Casticimo
  • Publication number: 20230012958
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 19, 2023
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han
  • Publication number: 20230015504
    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu
  • Publication number: 20220384505
    Abstract: A semiconductor device has a substrate. A semiconductor die including a photosensitive circuit is disposed over the substrate. A shield is disposed over the substrate and semiconductor die with a first opening of the shield disposed over the photosensitive circuit. An outer section of the shield is attached to the substrate and includes a second opening. An encapsulant is deposited over the substrate and semiconductor die. The encapsulant extends into the first opening and a first area between the shield and substrate while a second area over the photosensitive circuit remains devoid of the encapsulant.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 1, 2022
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: Emmanuel Espiritu, Il Kwon Shim, Jeffrey Punzalan, Teddy Joaquin Carreon
  • Patent number: 11488932
    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 1, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu