Abstract: A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: Provided is a hybrid flash memory device, a memory system, and a method of controlling errors. The hybrid flash memory device includes a data storage block with first and second data storage regions of flash memory cells, and error control block implementing first and second error control schemes, such that a data access operation directed to data stored in the first data storage region selects the first error control scheme, and a data access operation directed to data stored in the second data storage region selects the second error control scheme.

Abstract: An embodiment of a differential output driver includes a driver to generate an inverted output signal in response to an input signal and a first control signal, and to further generate an output signal in response to an inverted input signal and a second control signal. The differential output driver also includes a controller to generate the first control signal and the second control signal in response to detecting a voltage difference between a first detected voltage difference between a reference voltage and the output signal, and a second detected voltage difference between the reference voltage and the inverted output signal.

Abstract: A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

Abstract: In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: A speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: An embodiment of a differential output driver includes a driver to generate an inverted output signal in response to an input signal and a first control signal, and to further generate an output signal in response to an inverted input signal and a second control signal. The differential output driver also includes a controller to generate the first control signal and the second control signal in response to detecting a voltage difference between a first detected voltage difference between a reference voltage and the output signal, and a second detected voltage difference between the reference voltage and the inverted output signal.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of external electric power. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command.

Abstract: A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of external electric power. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command.

Abstract: A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of external electric power. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of external electric power. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command.

Abstract: The internal clock signal generating circuit of the present invention includes a pulse generation circuit for receiving a reference clock signal which is generated in response to an external clock signal, and generating an internal clock signal. The pulse generation circuit includes a pulse generation unit for generating a pulse signal which is activated in response to a rising edge of a first delay signal obtained by delaying the reference clock signal by a first delay time, and deactivated in response to a falling edge of a second delay signal obtained by delaying the reference clock signal by a second delay time which is shorter than the first delay time, and a driving unit for generating the internal clock signal which is activated in response to a falling edge of the reference clock signal and deactivated in response to a rising edge of the pulse signal.

Abstract: Integrated circuit memory devices include a control circuit that generates an active first control pulse (e.g., PR) having a first duration, in response to an active strobe pulse (e.g., /RAS) that may be generated during a data reading operation. To improve the reliability of the data reading operation and any subsequent data restore operation, particularly when the duration of the active strobe pulse is relatively short, a pulse width extension circuit is provided. The pulse width extension circuit converts the active first control pulse into an active second control pulse (e.g., PAIVCE2) having a second duration greater than the first duration. This active second control pulse is then provided as a control input to an internal voltage generator. The internal voltage generator is provided to drive a first supply signal line (e.g., AIVC2) at a first supply voltage in response to the active second control pulse.

Abstract: An internal clock signal generator of a synchronous memory device is provided. The internal clock signal generator includes first and second inverting portions, a delay portion, first and second switching portions, and first and second logic portions also called input and output logic circuits, respectively. The first inverting portion inverts an external clock signal. The second inverting portion inverts an output signal of the first inverting portion. The delay portion delays an output signal of the second inverting portion. The first switching portion gates an output signal of the delay portion in response to a first control signal. The second switching portion gates the output signal of the second inverting portion in response to a second control signal. The first or input logic portion performs a logic operation with respect to signals input from an external source and outputting the first and second control signals.