Patents by Inventor Il-Min Yi

Il-Min Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Decision feedback equalizer
    Patent number: 11336491
    Abstract: An amplifier output from an amplifier to an SR latch is used as a feedback signal through a buffer. An adder having a combination of an addition unit and an xh block is provided within the amplifier and transmits a feedback signal (analog signal) generated from the feedback signal FBD (digital signal) by the xh block to the addition unit and adds it to an output from a latch block. In the amplifier, the operation for adding the output from the latch block and the feedback signal occurs during a latch operation in the latch block.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 17, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka
  • Analog-digital converter
    Patent number: 11258454
    Abstract: An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2L reference times corresponding to 2L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka
  • Analog-Digital Converter
    Publication number: 20210367608
    Abstract: An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2L reference times corresponding to 2L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.
    Type: Application
    Filed: October 15, 2019
    Publication date: November 25, 2021
    Inventors: Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka
  • Decision Feedback Equalizer
    Publication number: 20210288846
    Abstract: An amplifier output from an amplifier to an SR latch is used as a feedback signal through a buffer. An adder having a combination of an addition unit and an xh block is provided within the amplifier and transmits a feedback signal (analog signal) generated from the feedback signal FBD (digital signal) by the xh block to the addition unit and adds it to an output from a latch block. In the amplifier, the operation for adding the output from the latch block and the feedback signal occurs during a latch operation in the latch block.
    Type: Application
    Filed: September 11, 2019
    Publication date: September 16, 2021
    Inventors: Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka