Abstract: A device of providing an investment value evaluation service according to one embodiment of the present disclosure may include a preprocessing module that processes financial data for each company or asset collected from a market server to generate training data including figures for each preset financial indicator; an analysis module that is constructed through the training of a preset machine learning model using the training data to predict a value evaluation index for each company or asset, and output analysis data based on the predicted value evaluation index; and a service providing module that processes analysis data for a specific company or asset output from the analysis module according to an analysis request from a user terminal to provide investment value evaluation data to the user terminal, wherein the value evaluation index is a fair price representing an upside potential in the value of a company or asset according to the figures for each financial indicator compared to a current price.

Abstract: A semiconductor device includes a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip. The first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.

Abstract: A semiconductor device includes a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip. The first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.

Abstract: A hub chiplet includes a functional module. The hub chiplet includes a top connection module formed on a cross-section of the hub chiplet in a first direction; a bottom connection module formed on a cross-section of the hub chiplet in a second direction opposite to the first direction; a left connection module formed on a cross-section of the hub chiplet in a third direction perpendicular to a first straight line connecting the top connection module to the bottom connection module; and a right connection module formed on a cross-section of the hub chiplet in a fourth direction that is perpendicular to the first straight line and is opposite to the third direction. The top connection module is connectable to the bottom connection module through a device-to-device (D2D) connection, and the left connection module is connectable to the right connection module through the D2D connection.

Abstract: A semiconductor device includes a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip. The first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.

Abstract: The present disclosure relates to an immuno-potentiating composition, more specifically to a composition containing an enzymatic extract of deer antler with excellent NK cell activity as an active ingredient, which exhibits immuno-potentiating effect by proliferating immune cells and particularly enhancing NK cell activity and, as such, can be used as a food composition and further as a health functional food or pharmaceutical composition for immuno-potentiation.

Abstract: A display device including a pixel electrode disposed in an opening area; a common electrode of which at least a region is disposed to be overlapped with the pixel electrode; a gate line extending along a first direction in a non-opening area surrounding the opening area and transmitting a gate signal to the pixel electrode; a data line extending along a second direction different from the first direction in the non-opening area, and transmitting a data signal to the pixel electrode; and a dummy line disposed to be overlapped with the data line in the non-opening area and electrically connected to the common electrode.

Abstract: A display device including a pixel electrode disposed in an opening area; a common electrode of which at least a region is disposed to be overlapped with the pixel electrode; a gate line extending along a first direction in a non-opening area surrounding the opening area and transmitting a gate signal to the pixel electrode; a data line extending along a second direction different from the first direction in the non-opening area, and transmitting a data signal to the pixel electrode; and a dummy line disposed to be overlapped with the data line in the non-opening area and electrically connected to the common electrode.

Abstract: A display device including a pixel electrode disposed in an opening area; a common electrode of which at least a region is disposed to be overlapped with the pixel electrode; a gate line extending along a first direction in a non-opening area surrounding the opening area and transmitting a gate signal to the pixel electrode; a data line extending along a second direction different from the first direction in the non-opening area, and transmitting a data signal to the pixel electrode; and a dummy line disposed to be overlapped with the data line in the non-opening area and electrically connected to the common electrode.

Abstract: A memory may include: a pseudorandom number generator suitable for generating a pseudorandom number using an initial value transferred from a memory controller; an access key register suitable for storing an access key transferred from the memory controller; a counter suitable for counting the number of times that the access key register is updated to generate an update number; a logic operation circuit suitable for generating an authentication key by performing a logic operation on the pseudorandom number and the update number; a comparison circuit suitable for comparing the access key and the authentication key; and a security area to which access is allowed when the comparison result of the comparison circuit indicates that the access key and the authentication key are the same.

Abstract: A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, and each of the plurality of sub-arrays has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing column address information of a repaired main column of one of the plurality of sub-arrays and address information of a repaired main column of another of the plurality of sub-arrays into at least one of the plurality of storage units included in the spare column remap storage.

Abstract: A data processing system includes a memory device; buffer entries each including a plurality of slabs; a prefetch circuit configured to prefetch data from the memory device and store the data in the buffer entries; and processing circuits respectively corresponding to the slabs, each processing circuit being configured to sequentially demand-fetch and process data stored in corresponding slabs in the buffer entries, wherein each processing circuit checks, when demand-fetching data from a first slab among corresponding slabs, a prefetch trigger bit of a first buffer entry in which the first slab is included, determines, when it is determined that the prefetch trigger bit is set, whether all data stored in the slabs included in a second buffer entry is demand-fetched, and triggers, when it is determined that all the data is demand-fetched, the prefetch circuit to perform prefetch of subsequent data to the second buffer entry.

Abstract: A memory may include: a pseudorandom number generator suitable for generating a pseudorandom number using an initial value transferred from a memory controller; an access key register suitable for storing an access key transferred from the memory controller; a counter suitable for counting the number of times that the access key register is updated to generate an update number; a logic operation circuit suitable for generating an authentication key by performing a logic operation on the pseudorandom number and the update number; a comparison circuit suitable for comparing the access key and the authentication key; and a security area to which access is allowed when the comparison result of the comparison circuit indicates that the access key and the authentication key are the same.

Abstract: A display device including a pixel electrode disposed in an opening area; a common electrode of which at least a region is disposed to be overlapped with the pixel electrode; a gate line extending along a first direction in a non-opening area surrounding the opening area and transmitting a gate signal to the pixel electrode; a data line extending along a second direction different from the first direction in the non-opening area, and transmitting a data signal to the pixel electrode; and a dummy line disposed to be overlapped with the data line in the non-opening area and electrically connected to the common electrode.

Abstract: A data processing system includes a memory device; buffer entries each including a plurality of slabs; a prefetch circuit configured to prefetch data from the memory device and store the data in the buffer entries; and processing circuits respectively corresponding to the slabs, each processing circuit being configured to sequentially demand-fetch and process data stored in corresponding slabs in the buffer entries, wherein each processing circuit checks, when demand-fetching data from a first slab among corresponding slabs, a prefetch trigger bit of a first buffer entry in which the first slab is included, determines, when it is determined that the prefetch trigger bit is set, whether all data stored in the slabs included in a second buffer entry is demand-fetched, and triggers, when it is determined that all the data is demand-fetched, the prefetch circuit to perform prefetch of subsequent data to the second buffer entry.

Abstract: A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, and each of the plurality of sub-arrays has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing column address information of a repaired main column of one of the plurality of sub-arrays and address information of a repaired main column of another of the plurality of sub-arrays into at least one of the plurality of storage units included in the spare column remap storage.

Abstract: A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, each of which has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing address information of the main columns repaired using the plurality of spare columns. At least one of the plurality of storage units included in the spare column remap storage is provided to store address information of the main column repaired in one of the plurality of sub-arrays and address information of the main column repaired in another of the plurality of sub-arrays.

Abstract: A memory system includes a first memory device, a second memory device, and a controller. The second memory device has a write endurance which is higher than a write endurance of the first memory device. The controller performs an error correction process on original data outputted from a host to generate a codeword including the original data and parity data. The controller separates the codeword into the original data and the parity data to write the separated original data into the first memory device and to write the separated parity data into the second memory device.

Abstract: A memory system may include a first cache memory including a plurality of regions, which are accessed using a first address, and in each of which an indication of whether cached data is present and a second address are stored. A memory system may also include a second cache memory configured to be accessed using the second address stored in an accessed region of the first cache memory when, as a result of an access of the first cache memory, cached data is present. Still further, a memory system may include a main memory configured to be accessed using the first address when, as the result of the access of the first cache memory, cached data is not present.

Abstract: A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.