Abstract: A method for performing sidelink groupcast transmission by a transmission terminal includes the steps of: classifying reception terminals belonging to a subject group into two or more subgroups; allocating different groupcast feedback schemes to the two or more subgroups; performing groupcast transmission to the reception terminals; and receiving feedback information from terminals belonging to at least one subgroup among the two or more subgroups according to the different groupcast feedback schemes.

Abstract: An operation method of an IAB node in a communication system may comprise: measuring a power difference between a first signal received from a first node and a second signal received from a second node; controlling a transmit power of each of the first node and the second node based on the power difference; generating scheduling information for allowing the first node and the second node to simultaneously transmit signals; transmitting the scheduling information to the first node and the second node; and receiving signals that the first node and the second node simultaneously transmit according to the scheduling information by using the transmit power.

Abstract: A rendering method, medium and apparatus for sequentially performing one or more third raster operations to test whether a fragment can be displayed as a pixel after sequentially performing one or more second raster operations to test whether the fragment can be displayed as the pixel, so as to provide efficient power consumption and rapid completion of rendering.

Abstract: A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.

Abstract: A rendering method, medium and apparatus for sequentially performing one or more third raster operations to test whether a fragment can be displayed as a pixel after sequentially performing one or more second raster operations to test whether the fragment can be displayed as the pixel, so as to provide efficient power consumption and rapid completion of rendering.

Abstract: A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.

Abstract: A graphics system and a memory device for three-dimensional (3D) graphics acceleration, and a method for 3D graphics processing, are provided. In a memory device in a graphics system for 3D graphics processing, a memory structure includes a first memory area allocated to a texture buffer for storing texture data, and a second memory area allocated to a frame buffer for storing frame data in pixels. A comparator controls the memory structure to operate as the texture buffer if an input address to the memory structure indicates the first memory area and controls the memory structure to operate as the frame buffer if the input address indicates the second memory area. If the memory structure operates as the frame buffer, an ALU performs depth comparison or alpha-blending on input frame data and frame data read from the frame buffer.

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.

Abstract: A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

Abstract: A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.